2010-02-23 03:29:05 +08:00
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#------------------------------------------------------------------------------
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# Run the simulation testbench in ModelSim: recompile both Verilog source
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# files, then start the simulation, add a lot of signals to the waveform
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# viewer, and run. I should (TODO) fix the absolute paths at some point.
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#
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# Jonathan Westhues, Mar 2006
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#------------------------------------------------------------------------------
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vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
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vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
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vsim work.fpga_tb
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add wave sim:/fpga_tb/adc_clk
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add wave sim:/fpga_tb/adc_d
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add wave sim:/fpga_tb/pwr_lo
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add wave sim:/fpga_tb/ssp_clk
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add wave sim:/fpga_tb/ssp_frame
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add wave sim:/fpga_tb/ssp_din
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add wave sim:/fpga_tb/ssp_dout
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add wave sim:/fpga_tb/dut/clk_lo
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add wave sim:/fpga_tb/dut/pck_divider
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add wave sim:/fpga_tb/dut/carrier_divider_lo
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add wave sim:/fpga_tb/dut/conf_word
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run 30000
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