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https://github.com/Proxmark/proxmark3.git
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More robust iso14443a sniffing/simulation functions by
- iso14443a.c: less strict Miller/Manchester decoders - FPGA hi_iso14443a.v: syncing on external readers' clock when simulating and sniffing.
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@ -236,6 +236,15 @@ bool RAMFUNC LogTrace(const uint8_t * btBytes, uint8_t iLen, uint32_t timestamp,
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//-----------------------------------------------------------------------------
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static tUart Uart;
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// Lookup-Table to decide if 4 raw bits are a modulation.
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// We accept two or three consecutive "0" in any position with the rest "1"
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const bool Mod_Miller_LUT[] = {
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TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
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TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
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};
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#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
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#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
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void UartReset()
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{
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Uart.state = STATE_UNSYNCD;
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@ -249,7 +258,7 @@ void UartReset()
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Uart.endTime = 0;
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}
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inline RAMFUNC Modulation_t MillerModulation(uint8_t b)
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/* inline RAMFUNC Modulation_t MillerModulation(uint8_t b)
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{
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// switch (b & 0x88) {
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// case 0x00: return MILLER_MOD_BOTH_HALVES;
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@ -265,7 +274,7 @@ inline RAMFUNC Modulation_t MillerModulation(uint8_t b)
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default: return MOD_NOMOD;
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}
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}
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*/
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// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
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static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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{
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@ -293,14 +302,18 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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if (Uart.syncBit != 0xFFFF) {
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Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
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Uart.startTime -= Uart.syncBit;
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Uart.endTime = Uart.startTime;
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Uart.state = STATE_START_OF_COMMUNICATION;
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}
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}
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} else {
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switch (MillerModulation(Uart.twoBits >> Uart.syncBit)) {
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case MOD_FIRST_HALF: // Sequence Z = 0
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if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
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if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
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UartReset();
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Uart.highCnt = 6;
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} else { // Modulation in first half = Sequence Z = logic "0"
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if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
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UartReset();
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Uart.highCnt = 6;
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@ -317,8 +330,9 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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Uart.shiftReg = 0;
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}
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}
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break;
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case MOD_SECOND_HALF: // Sequence X = 1
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}
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} else {
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if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
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Uart.bitCount++;
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Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
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Uart.state = STATE_MILLER_X;
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@ -330,15 +344,14 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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Uart.bitCount = 0;
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Uart.shiftReg = 0;
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}
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break;
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case MOD_NOMOD: // no modulation in both halves - Sequence Y
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} else { // no modulation in both halves - Sequence Y
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if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
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Uart.state = STATE_UNSYNCD;
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if(Uart.len == 0 && Uart.bitCount > 0) { // if we decoded some bits
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Uart.shiftReg >>= (9 - Uart.bitCount); // add them to the output
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Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
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Uart.parityBits <<= 1; // no parity bit - add "0"
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Uart.bitCount--; // last "0" was part of the EOC sequence
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Uart.bitCount--; // last "0" was part of the EOC sequence
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}
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return TRUE;
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}
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@ -357,11 +370,7 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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Uart.shiftReg = 0;
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}
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}
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break;
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case MOD_BOTH_HALVES: // Error
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UartReset();
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Uart.highCnt = 6;
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return FALSE;
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}
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}
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}
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@ -388,9 +397,11 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
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// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
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static tDemod Demod;
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// Lookup-Table to decide if 4 raw bits are a modulation.
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// We accept three or four consecutive "1" in any position
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const bool Mod_Manchester_LUT[] = {
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FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE,
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FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
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FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
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FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE
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};
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#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
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@ -434,7 +445,7 @@ static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non
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else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
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else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
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else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
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if (Demod.syncBit < 8) {
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if (Demod.syncBit != 0xFFFF) {
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Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
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Demod.startTime -= Demod.syncBit;
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Demod.bitCount = offset; // number of decoded data bits
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@ -473,15 +484,17 @@ static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non
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}
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Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
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} else { // no modulation in both halves - End of communication
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if(Demod.bitCount > 0) { // if we decoded bits
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Demod.shiftReg >>= (9 - Demod.bitCount); // add the remaining decoded bits to the output
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Demod.output[Demod.len++] = Demod.shiftReg & 0xff;
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// No parity bit, so just shift a 0
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Demod.parityBits <<= 1;
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if (Demod.len > 0 || Demod.bitCount > 0) { // received something
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if(Demod.bitCount > 0) { // if we decoded bits
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Demod.shiftReg >>= (9 - Demod.bitCount); // add the remaining decoded bits to the output
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Demod.output[Demod.len++] = Demod.shiftReg & 0xff;
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// No parity bit, so just shift a 0
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Demod.parityBits <<= 1;
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}
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return TRUE; // we are finished with decoding the raw data sequence
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} else { // nothing received. Start over
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DemodReset();
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}
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Demod.state = DEMOD_UNSYNCD; // start from the beginning
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Demod.twoBits = 0;
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return TRUE; // we are finished with decoding the raw data sequence
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}
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}
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BIN
fpga/fpga.bit
BIN
fpga/fpga.bit
Binary file not shown.
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@ -35,7 +35,7 @@ reg ssp_frame;
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wire adc_clk;
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assign adc_clk = ck_1356meg;
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reg after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3, after_hysteresis_prev4;
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reg after_hysteresis, pre_after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3, after_hysteresis_prev4;
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reg [11:0] has_been_low_for;
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reg [8:0] saw_deep_modulation;
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reg [2:0] deep_counter;
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@ -45,6 +45,8 @@ always @(negedge adc_clk)
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begin
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if(& adc_d[7:6]) after_hysteresis <= 1'b1; // adc_d >= 196 (U >= 3,28V) -> after_hysteris = 1
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else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0; // if adc_d <= 15 (U <= 1,13V) -> after_hysteresis = 0
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pre_after_hysteresis <= after_hysteresis;
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if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
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begin
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@ -122,6 +124,7 @@ reg mod_sig, mod_sig_coil;
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reg temp_buffer_reset;
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reg sendbit;
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reg [3:0] sub_carrier_cnt;
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reg[3:0] reader_falling_edge_time;
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// ADC data appears on the rising edge, so sample it on the falling edge
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always @(negedge adc_clk)
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@ -244,13 +247,42 @@ begin
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sendbit = 1'b0;
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end
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// check timing of a falling edge in reader signal
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if (pre_after_hysteresis && ~after_hysteresis)
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reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
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else
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reader_falling_edge_time[3:0] <= 4'd8;
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// sync clock to external reader's clock:
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if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_MOD || mod_type == `TAGSIM_LISTEN))
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begin
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// adjust clock if necessary:
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if (reader_falling_edge_time < 4'd8 && reader_falling_edge_time > 4'd1)
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begin
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negedge_cnt <= negedge_cnt; // freeze time
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end
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else if (reader_falling_edge_time == 4'd8)
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begin
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negedge_cnt <= negedge_cnt + 1; // the desired state. Advance as usual;
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end
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else
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begin
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negedge_cnt[3:0] <= 4'd15; // time warp
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end
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reader_falling_edge_time <= 4'd8; // only once per detected rising edge
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end
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//------------------------------------------------------------------------------------------------------------------------------------------
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// Prepare 8 Bits to communicate to ARM
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// in SNIFFER mode: 4 Bits data sniffed as Tag, 4 Bits data sniffed as Reader
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if(mod_type == `SNIFFER)
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if (negedge_cnt == 7'd63)
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begin
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if (negedge_cnt == 7'd63)
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if (mod_type == `SNIFFER)
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begin
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if(deep_modulation) // a reader is sending (or there's no field at all)
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begin
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@ -259,34 +291,32 @@ begin
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else
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begin
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to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,bit1,bit2,bit3,bit4};
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end
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end
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negedge_cnt <= 0;
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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end
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end
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else
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// other modes: 8 Bits info on queue delay
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end
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else if(negedge_cnt == 7'd127)
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begin
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if(negedge_cnt == 7'd127)
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if (mod_type == `TAGSIM_MOD)
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begin
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if (mod_type == `TAGSIM_MOD)
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begin
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to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]};
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end
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else
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begin
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to_arm[7:0] <= 8'd0;
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end
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to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]};
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negedge_cnt <= 0;
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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to_arm[7:0] <= 8'd0;
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negedge_cnt <= negedge_cnt + 1;
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end
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end
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else
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begin
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negedge_cnt <= negedge_cnt + 1;
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end
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if(negedge_cnt == 7'd1)
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begin
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