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https://github.com/Proxmark/proxmark3.git
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adjust lf simulation - fix one bug + attempt... (#369)
... to speed up the loops waiting for carrier signal to go high or low by only checking for a halt (button press or usbpol) every 1000th loop iteration. some users were experiencing modulating reactions to be too slow.
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@ -387,7 +387,8 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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int i;
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uint8_t *tab = BigBuf_get_addr();
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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//note this may destroy the bigbuf so be sure this is called before now...
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
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@ -401,13 +402,19 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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i = 0;
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for(;;) {
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//wait until SSC_CLK goes HIGH
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int ii = 0;
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while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
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if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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DbpString("Stopped");
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return;
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//only check every 1000th time (usb_poll_validate_length on some systems was too slow)
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if ( ii == 1000 ) {
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if (BUTTON_PRESS() || usb_poll_validate_length() ) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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DbpString("Stopped");
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return;
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}
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ii=0;
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}
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WDT_HIT();
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ii++;
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}
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if (ledcontrol)
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LED_D_ON();
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@ -419,14 +426,20 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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if (ledcontrol)
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LED_D_OFF();
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ii=0;
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//wait until SSC_CLK goes LOW
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while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
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if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
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DbpString("Stopped");
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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return;
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//only check every 1000th time (usb_poll_validate_length on some systems was too slow)
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if ( ii == 1000 ) {
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if (BUTTON_PRESS() || usb_poll_validate_length() ) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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DbpString("Stopped");
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return;
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}
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ii=0;
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}
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WDT_HIT();
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ii++;
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}
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i++;
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@ -545,6 +558,9 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
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DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
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return;
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}
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// set LF so we don't kill the bigbuf we are setting with simulation data.
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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fc(0,&n);
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// special start of frame marker containing invalid bit sequences
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fc(8, &n); fc(8, &n); // invalid
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@ -595,6 +611,9 @@ void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
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uint8_t clk = arg2 & 0xFF;
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uint8_t invert = (arg2 >> 8) & 1;
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// set LF so we don't kill the bigbuf we are setting with simulation data.
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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for (i=0; i<size; i++){
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if (BitStream[i] == invert){
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fcAll(fcLow, &n, clk, &modCnt);
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@ -670,6 +689,9 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
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uint8_t separator = arg2 & 1;
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uint8_t invert = (arg2 >> 8) & 1;
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// set LF so we don't kill the bigbuf we are setting with simulation data.
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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if (encoding==2){ //biphase
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uint8_t phase=0;
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for (i=0; i<size; i++){
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@ -741,6 +763,9 @@ void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
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uint8_t carrier = arg1 & 0xFF;
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uint8_t invert = arg2 & 0xFF;
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uint8_t curPhase = 0;
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// set LF so we don't kill the bigbuf we are setting with simulation data.
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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for (i=0; i<size; i++){
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if (BitStream[i] == curPhase){
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pskSimBit(carrier, &n, clk, &curPhase, FALSE);
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