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https://github.com/Proxmark/proxmark3.git
synced 2025-02-26 00:25:24 +08:00
adjust lf t55xx read commands
seems to make them a lot more accurate for me
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d10e08ae6e
commit
f4eadf8a50
3 changed files with 92 additions and 30 deletions
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@ -1085,6 +1085,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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#define T55x7_MODULATION_FSK2a 0x00007000
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#define T55x7_MODULATION_MANCHESTER 0x00008000
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#define T55x7_MODULATION_BIPHASE 0x00010000
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#define T55x7_MODULATION_DIPHASE 0x00018000
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#define T55x7_BITRATE_RF_8 0
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#define T55x7_BITRATE_RF_16 0x00040000
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#define T55x7_BITRATE_RF_32 0x00080000
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@ -1126,7 +1127,9 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
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#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
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#define T55xx_READ_UPPER_THRESHOLD 128+40 // 50
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#define T55xx_READ_TOL 5
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//#define T55xx_READ_LOWER_THRESHOLD 128-40 //-50
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// Write one bit to card
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void T55xxWriteBit(int bit)
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{
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@ -1148,7 +1151,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
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// Set up FPGA, 125kHz
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// Wait for config.. (192+8190xPOW)x8 == 67ms
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LFSetupFPGAForADC(0, true);
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LFSetupFPGAForADC(95, true);
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// Now start writting
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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@ -1184,7 +1187,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
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void TurnReadLFOn(){
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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SpinDelayUs(8*150);
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SpinDelayUs(50*8); //155*8
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}
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@ -1196,13 +1199,26 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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uint16_t bufferlength = BigBuf_max_traceLen();
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if ( bufferlength > T55xx_SAMPLES_SIZE )
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bufferlength = T55xx_SAMPLES_SIZE;
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Block &= 0x7; //make sure block is at max 7
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// Clear destination buffer before sending the command
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memset(dest, 0x80, bufferlength);
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// Set up FPGA, 125kHz
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// Wait for config.. (192+8190xPOW)x8 == 67ms
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LFSetupFPGAForADC(0, true);
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LFSetupFPGAForADC(95, true);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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// Give it a bit of time for the resonant antenna to settle.
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//SpinDelayUs(8*200); //192FC
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SpinDelay(50);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayUs(START_GAP);
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@ -1224,16 +1240,34 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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TurnReadLFOn();
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// Now do the acquisition
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i = 0;
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bool startFound = false;
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bool highFound = false;
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uint8_t curSample = 0;
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uint8_t firstSample = 0;
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for(;;) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
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AT91C_BASE_SSC->SSC_THR = 0x43;
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LED_D_ON();
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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LED_D_OFF();
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if (i >= bufferlength) break;
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curSample = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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// find first high sample
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if (!startFound && curSample > T55xx_READ_UPPER_THRESHOLD) {
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if (curSample > firstSample) firstSample = curSample;
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highFound = true;
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} else if (!highFound) {
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continue;
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}
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// skip until samples begin to change
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if (startFound || curSample < firstSample-T55xx_READ_TOL){
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if (!startFound) dest[i++] = firstSample;
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startFound = true;
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dest[i++] = curSample;
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LED_D_OFF();
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if (i >= bufferlength) break;
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}
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}
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}
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@ -1266,17 +1300,34 @@ void T55xxReadTrace(void){
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TurnReadLFOn();
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// Now do the acquisition
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bool startFound = false;// false;
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bool highFound = false;
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uint8_t curSample = 0;
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uint8_t firstSample = 0;
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for(;;) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
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AT91C_BASE_SSC->SSC_THR = 0x43;
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LED_D_ON();
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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LED_D_OFF();
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curSample = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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// find first high sample
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if (!startFound && curSample > T55xx_READ_UPPER_THRESHOLD) {
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if (curSample > firstSample) firstSample = curSample;
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highFound = true;
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} else if (!highFound) {
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continue;
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}
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if (i >= bufferlength) break;
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// skip until samples begin to change
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if (startFound || curSample < firstSample-T55xx_READ_TOL){
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if (!startFound) dest[i++] = firstSample;
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startFound = true;
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dest[i++] = curSample;
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LED_D_OFF();
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if (i >= bufferlength) break;
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}
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}
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}
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@ -270,8 +270,8 @@ bool DecodeT55xxBlock(){
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DemodBufferLen = 0x00;
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//trim 1/2 a clock from beginning
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snprintf(cmdStr, sizeof(buf),"%d", bitRate[config.bitrate]/2 );
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CmdLtrim(cmdStr);
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//snprintf(cmdStr, sizeof(buf),"%d", bitRate[config.bitrate]/2 );
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//CmdLtrim(cmdStr);
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switch( config.modulation ){
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case DEMOD_FSK:
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snprintf(cmdStr, sizeof(buf),"%d %d", bitRate[config.bitrate], config.inverted );
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@ -333,7 +333,7 @@ int CmdT55xxDetect(const char *Cmd){
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// detect configuration?
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bool tryDetectModulation(){
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char cmdStr[8] = {0};
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//char cmdStr[8] = {0};
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uint8_t hits = 0;
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t55xx_conf_block_t tests[15];
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int bitRate=0;
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@ -341,8 +341,8 @@ bool tryDetectModulation(){
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save_restoreGB(1);
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if (GetFskClock("", FALSE, FALSE)){
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fskClocks(&fc1, &fc2, &clk, FALSE);
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sprintf(cmdStr,"%d", clk/2);
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CmdLtrim(cmdStr);
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//sprintf(cmdStr,"%d", clk/2);
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//CmdLtrim(cmdStr);
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if ( FSKrawDemod("0 0", FALSE) && test(DEMOD_FSK, &tests[hits].offset, &bitRate)){
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tests[hits].modulation = DEMOD_FSK;
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if (fc1==8 && fc2 == 5)
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@ -369,8 +369,8 @@ bool tryDetectModulation(){
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} else {
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clk = GetAskClock("", FALSE, FALSE);
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if (clk>0) {
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sprintf(cmdStr,"%d", clk/2);
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CmdLtrim(cmdStr);
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//sprintf(cmdStr,"%d", clk/2);
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//CmdLtrim(cmdStr);
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if ( ASKDemod("0 0 0", FALSE, FALSE, 1) && test(DEMOD_ASK, &tests[hits].offset, &bitRate)) {
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tests[hits].modulation = DEMOD_ASK;
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tests[hits].bitrate = bitRate;
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@ -404,8 +404,8 @@ bool tryDetectModulation(){
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save_restoreGB(0);
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clk = GetNrzClock("", FALSE, FALSE);
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if (clk>0) {
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sprintf(cmdStr,"%d", clk/2);
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CmdLtrim(cmdStr);
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//sprintf(cmdStr,"%d", clk/2);
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//CmdLtrim(cmdStr);
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if ( NRZrawDemod("0 0 1", FALSE) && test(DEMOD_NRZ, &tests[hits].offset, &bitRate)) {
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tests[hits].modulation = DEMOD_NRZ;
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tests[hits].bitrate = bitRate;
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@ -427,9 +427,9 @@ bool tryDetectModulation(){
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save_restoreGB(0);
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clk = GetPskClock("", FALSE, FALSE);
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if (clk>0) {
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PrintAndLog("clk %d",clk);
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sprintf(cmdStr,"%d", clk/2);
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CmdLtrim(cmdStr);
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//PrintAndLog("clk %d",clk);
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//sprintf(cmdStr,"%d", clk/2);
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//CmdLtrim(cmdStr);
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if ( PSKDemod("0 0 1", FALSE) && test(DEMOD_PSK1, &tests[hits].offset, &bitRate)) {
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tests[hits].modulation = DEMOD_PSK1;
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tests[hits].bitrate = bitRate;
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@ -369,7 +369,9 @@ size_t fsk_wave_demod(uint8_t * dest, size_t size, uint8_t fchigh, uint8_t fclow
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if (fclow==0) fclow=8;
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//set the threshold close to 0 (graph) or 128 std to avoid static
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uint8_t threshold_value = 123;
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size_t preLastSample = 0;
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size_t LastSample = 0;
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size_t currSample = 0;
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// sync to first lo-hi transition, and threshold
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// Need to threshold first sample
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@ -389,13 +391,22 @@ size_t fsk_wave_demod(uint8_t * dest, size_t size, uint8_t fchigh, uint8_t fclow
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// Check for 0->1 transition
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if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
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if ((idx-last_transition)<(fclow-2)){ //0-5 = garbage noise
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preLastSample = LastSample;
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LastSample = currSample;
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currSample = idx-last_transition;
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if (currSample < (fclow-2)){ //0-5 = garbage noise
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//do nothing with extra garbage
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} else if ((idx-last_transition) < (fchigh-1)) { //6-8 = 8 waves
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} else if (currSample < (fchigh-1)) { //6-8 = 8 sample waves
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if (LastSample > (fchigh-2) && preLastSample < (fchigh-1)){
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dest[numBits-1]=1; //correct last 9 wave surrounded by 8 waves
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}
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dest[numBits++]=1;
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} else if ((idx-last_transition) > (fchigh+1) && !numBits) { //12 + and first bit = garbage
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} else if (currSample > (fchigh+1) && !numBits) { //12 + and first bit = garbage
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//do nothing with beginning garbage
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} else { //9+ = 10 waves
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} else if (currSample == (fclow+1) && LastSample == (fclow-1)) { // had a 7 then a 9 should be two 8's
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dest[numBits++]=1;
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} else { //9+ = 10 sample waves
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dest[numBits++]=0;
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}
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last_transition = idx;
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