* merge cmd.c into usb_cdc.c
* move back usb_cdc.[ch] to common/
* declare low level functions usb_read() and usb_write() and more functions as static
* use cmd_receive() in bootrom.c and appmain.c
* remove unused memory wasting csrTab[100] in usb_cdc.c
* replace more byte_t by uint8_t
* more whitespace fixes
* move cmd.[ch] and usb_cdc.[ch] to armsrc
* sorting out #includes
* replace byte_t by uint8_t
* some reformatting
* whitespace fixes
* (no functional changes)
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame
* get rid of most of the warnings when compiling the HF verilog sources
* refactoring the constants in Verilog sources
* Add raw HF signal plotting
* new fpga module hi_get_trace.v - store A/D converter output to circular buffer on FPGA
* new command 'hf plot' - pull data from FPGA and display it in Graph Window
* rework iso14443b device functions
* hf_read_rx_xcorr.v: transfer i/q pair in one 16bit frame
* hi_read_tx.v: invert ssp_dout. When nothing is transferred (ssp_dout=0), this results in no modulation (carrier on)
* adjust arm sources accordingly
* iso14443b.c: switch off carrier after hf 14b sri512read and hf 14b srix4kread
* iso14443b.c: fix DMA circular buffer handling
* FPGA Hi-Simulate: Formatted code
* FPGA Hi-Simulate: Fixed documantation
* FPGA Hi-Simulate: Freed up 4 LUTs
* FPGA Hi-Simulate: Added 212kHz SSP-Clock option
* Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
* Legic: Implemented RX and TX for card simulation
* Legic: Implemented setup phase for card simulation
* Legic: Implemented read command for card simulation
* Legic: Implemented write command for card simulation
* Legic: rewrite reader to use xcorrelation and precise timing
- Even tough Legic tags transmit just AM, receiving using
xcorrelation results in a significantly better signal
quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. prng and demodulation
- Having all times based on a fixed ts, results in perfect
rwd-tag synchronization without magic +/- calculations.
* hi_read_tx: remove jerry-riged hysteresis based receiver
- This feature got obsolete by a x-correlation based receiver.
* Legic: adjusted sampling to new ssp clock speed
- Sampling is 4 times faster and pipeline daly reduced to 1/4.
The new code samples each bit earyler to account for the
shorter pipeline. That introduced bit errors by leeking the
next bit into the current one.
* Legic: average 8 samples for better noise rejection.
* Update CHANGELOG.md
I have kept whatever copyright notices exist. Please add your own
copyright notice if you have made any nontrivial changes or additions to
the code. There are several files without any attribution, currently.
