* FPGA Hi-Simulate: Formatted code
* FPGA Hi-Simulate: Fixed documantation
* FPGA Hi-Simulate: Freed up 4 LUTs
* FPGA Hi-Simulate: Added 212kHz SSP-Clock option
* Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
* Legic: Implemented RX and TX for card simulation
* Legic: Implemented setup phase for card simulation
* Legic: Implemented read command for card simulation
* Legic: Implemented write command for card simulation
* Legic: rewrite reader to use xcorrelation and precise timing
- Even tough Legic tags transmit just AM, receiving using
xcorrelation results in a significantly better signal
quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. prng and demodulation
- Having all times based on a fixed ts, results in perfect
rwd-tag synchronization without magic +/- calculations.
* hi_read_tx: remove jerry-riged hysteresis based receiver
- This feature got obsolete by a x-correlation based receiver.
* Legic: adjusted sampling to new ssp clock speed
- Sampling is 4 times faster and pipeline daly reduced to 1/4.
The new code samples each bit earyler to account for the
shorter pipeline. That introduced bit errors by leeking the
next bit into the current one.
* Legic: average 8 samples for better noise rejection.
* Update CHANGELOG.md
I have kept whatever copyright notices exist. Please add your own
copyright notice if you have made any nontrivial changes or additions to
the code. There are several files without any attribution, currently.
