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3b2fee43ea
This is a new LF edge detection algorithm for the FPGA. - It uses a low-pass IIR filter to clean the signal (see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html) - The algorithm is able to detect consecutive peaks in the same direction - It uses an envelope follower to dynamically adjust the peak thresholds - The main threshold used in the envelope follower can be set from the ARM side fpga/lf_edge_detect.v, fpga/lp20khz_1MSa_iir_filter.v, fpga/min_max_tracker.v: New file. fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly. armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command. fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register. fpga/fpga_lf.bit: Update accordingly. fpga/tests: New directory for testbenches fpga/tests/Makefile: New file. It compiles the testbenches and runs all the tests by default (comparing with the golden output) fpga/tests/tb_lp20khz_1MSa_iir_filter.v, fpga/tests/tb_min_max_tracker.v, fpga/tests/tb_lf_edge_detect.v: New testbenches fpga/tests/plot_edgedetect.py: New script to plot the results from the edge detection tests. fpga/tests/tb_data: New directory for data and golden outputs
67 lines
2.2 KiB
Verilog
67 lines
2.2 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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//
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// There are two modes:
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// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
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// (resp. high) edge/peak is detected, with hysteresis
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// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
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// is detected.
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// That way you can detect two consecutive edges/peaks at the same level (L/H)
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//
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// Output:
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// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
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// - ssp_clk: cross_lo
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`include "lp20khz_1MSa_iir_filter.v"
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`include "lf_edge_detect.v"
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module lo_edge_detect(
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input pck0, input pck_divclk,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk,
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output ssp_frame, input ssp_dout, output ssp_clk,
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input cross_lo,
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output dbg,
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input lf_field,
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input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
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);
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wire tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
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// No logic, straight through.
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assign pwr_oe1 = 1'b0; // not used in LF mode
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assign pwr_oe2 = tag_modulation;
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assign pwr_oe3 = tag_modulation;
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assign pwr_oe4 = tag_modulation;
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assign ssp_clk = cross_lo;
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assign pwr_lo = reader_modulation;
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assign pwr_hi = 1'b0;
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// filter the ADC values
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wire data_rdy;
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wire [7:0] adc_filtered;
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assign adc_clk = pck0;
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lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
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// detect edges
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wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
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wire [7:0] max, min;
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wire edge_state, edge_toggle;
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lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
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max, min,
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high_threshold, highz_threshold, lowz_threshold, low_threshold,
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edge_state, edge_toggle);
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assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
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assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
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endmodule
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