AntiCat 1b902aa01a Legic Tag Simulator (#666) ... * FPGA Hi-Simulate: Formatted code * FPGA Hi-Simulate: Fixed documantation * FPGA Hi-Simulate: Freed up 4 LUTs * FPGA Hi-Simulate: Added 212kHz SSP-Clock option * Legic: Moved card simulator into separate file & cleaned interface. Reader and card simulation have almost no common code. Moreover the sim uses an SSP Clock at 212kHz for all timings to prevent any drifting from the PRNG. This clock speed is not available in reader simulation mode (SSP runs at up to 3.4MHz, and changes speed between TX and RX). For these reasons having the code in separate files makes it significantly cleaner. * Legic: Implemented RX and TX for card simulation * Legic: Implemented setup phase for card simulation * Legic: Implemented read command for card simulation * Legic: Implemented write command for card simulation		2018-09-09 16:40:20 +02:00
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tests	New LF edge detection algorithm + lowpass filter	2014-06-27 14:27:03 +02:00
clk_divider.v	THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.	2014-06-20 01:02:59 +02:00
fpga.ucf	- improved reader sensitivity for 14443a cards (FPGA change!)	2013-11-19 18:52:40 +00:00
fpga_hf.bit	Legic Tag Simulator (#666)	2018-09-09 16:40:20 +02:00
fpga_hf.v	revert removal of quarter frequency support for hi_read_rx_xcorr.v	2017-07-13 08:48:27 +02:00
fpga_lf.bit	- Correct little distraction on fpga/Makefile	2015-11-02 09:08:21 +01:00
fpga_lf.v	New LF edge detection algorithm + lowpass filter	2014-06-27 14:27:03 +02:00
go.bat	THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.	2014-06-20 01:02:59 +02:00
hi_iso14443a.v	fix hf mf sim:	2017-11-02 21:29:08 +01:00
hi_read_rx_xcorr.v	ISO15693 device side improvements (#652)	2018-08-15 14:03:20 +02:00
hi_read_tx.v	Legic: rewrite reader to use xcorrelation and precise timing (#654)	2018-08-20 22:29:34 +02:00
hi_simulate.v	Legic Tag Simulator (#666)	2018-09-09 16:40:20 +02:00
hi_sniffer.v	- Correct little distraction on fpga/Makefile	2015-11-02 09:08:21 +01:00
lf_edge_detect.v	New LF edge detection algorithm + lowpass filter	2014-06-27 14:27:03 +02:00
lo_edge_detect.v	fix: (issue #72) LF simulation didn't work with lo_edge_detect.v	2015-03-06 07:42:54 +01:00
lo_passthru.v	fpga/fpga_hf.v, fpga_lf.v, lo_edge_detect.v, lo_passthru.v, lo_read.v: copyright notice	2014-06-20 12:38:58 +02:00
lo_read.v	new command "lf snoop" to snoop raw ADC values	2014-06-21 21:33:54 +02:00
lo_simulate.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
lp20khz_1MSa_iir_filter.v	New LF edge detection algorithm + lowpass filter	2014-06-27 14:27:03 +02:00
Makefile	- Correct little distraction on fpga/Makefile	2015-11-02 09:08:21 +01:00
min_max_tracker.v	fpga/min_max_tracker.v: english	2014-06-27 23:28:56 +02:00
sim.tcl	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
testbed_fpga.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
testbed_hi_read_tx.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
testbed_hi_simulate.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
testbed_lo_read.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
testbed_lo_simulate.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
util.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
xst_hf.scr	THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.	2014-06-20 01:02:59 +02:00
xst_lf.scr	THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.	2014-06-20 01:02:59 +02:00