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3b2fee43ea
This is a new LF edge detection algorithm for the FPGA. - It uses a low-pass IIR filter to clean the signal (see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html) - The algorithm is able to detect consecutive peaks in the same direction - It uses an envelope follower to dynamically adjust the peak thresholds - The main threshold used in the envelope follower can be set from the ARM side fpga/lf_edge_detect.v, fpga/lp20khz_1MSa_iir_filter.v, fpga/min_max_tracker.v: New file. fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly. armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command. fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register. fpga/fpga_lf.bit: Update accordingly. fpga/tests: New directory for testbenches fpga/tests/Makefile: New file. It compiles the testbenches and runs all the tests by default (comparing with the golden output) fpga/tests/tb_lp20khz_1MSa_iir_filter.v, fpga/tests/tb_min_max_tracker.v, fpga/tests/tb_lf_edge_detect.v: New testbenches fpga/tests/plot_edgedetect.py: New script to plot the results from the edge detection tests. fpga/tests/tb_data: New directory for data and golden outputs |
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| .. | ||
| tests | ||
| clk_divider.v | ||
| fpga.ucf | ||
| fpga_hf.bit | ||
| fpga_hf.v | ||
| fpga_lf.bit | ||
| fpga_lf.v | ||
| go.bat | ||
| hi_iso14443a.v | ||
| hi_read_rx_xcorr.v | ||
| hi_read_tx.v | ||
| hi_simulate.v | ||
| lf_edge_detect.v | ||
| lo_edge_detect.v | ||
| lo_passthru.v | ||
| lo_read.v | ||
| lo_simulate.v | ||
| lp20khz_1MSa_iir_filter.v | ||
| Makefile | ||
| min_max_tracker.v | ||
| sim.tcl | ||
| testbed_fpga.v | ||
| testbed_hi_read_tx.v | ||
| testbed_hi_simulate.v | ||
| testbed_lo_read.v | ||
| testbed_lo_simulate.v | ||
| util.v | ||
| xst_hf.scr | ||
| xst_lf.scr | ||