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5ea2a24839
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame * get rid of most of the warnings when compiling the HF verilog sources * refactoring the constants in Verilog sources
55 lines
1.6 KiB
Plaintext
55 lines
1.6 KiB
Plaintext
# See the schematic for the pin assignment.
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NET "adc_d<0>" LOC = "P62" ;
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NET "adc_d<1>" LOC = "P60" ;
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NET "adc_d<2>" LOC = "P58" ;
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NET "adc_d<3>" LOC = "P57" ;
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NET "adc_d<4>" LOC = "P56" ;
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NET "adc_d<5>" LOC = "P55" ;
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NET "adc_d<6>" LOC = "P54" ;
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NET "adc_d<7>" LOC = "P53" ;
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NET "cross_hi" LOC = "P88" ;
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#NET "miso" LOC = "P40" ;
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "adc_clk" LOC = "P46" ;
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NET "adc_noe" LOC = "P47" ;
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NET "ck_1356meg" LOC = "P91" ;
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NET "ck_1356megb" LOC = "P93" ;
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NET "cross_lo" LOC = "P87" ;
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NET "dbg" LOC = "P22" ;
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NET "mosi" LOC = "P43" ;
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NET "ncs" LOC = "P44" ;
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NET "pck0" LOC = "P36" ;
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NET "pwr_hi" LOC = "P80" ;
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NET "pwr_lo" LOC = "P81" ;
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NET "pwr_oe1" LOC = "P82" ;
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NET "pwr_oe2" LOC = "P83" ;
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NET "pwr_oe3" LOC = "P84" ;
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NET "pwr_oe4" LOC = "P86" ;
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NET "spck" LOC = "P39" ;
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NET "ssp_clk" LOC = "P71" ;
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NET "ssp_din" LOC = "P32" ;
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NET "ssp_dout" LOC = "P34" ;
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NET "ssp_frame" LOC = "P31" ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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# definition of Clock nets:
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NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
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NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
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NET "pck0" TNM_NET = "clk_net_pck0" ;
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NET "spck" TNM_NET = "clk_net_spck" ;
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# Timing specs of clock nets:
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TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
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TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
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TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
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TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
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