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103 lines
3.7 KiB
Verilog
103 lines
3.7 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency read mode. In this case
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// we are generating the unmodulated low frequency carrier.
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// The A/D samples at that same rate and the result is serialized.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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module lo_read(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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lo_is_125khz, divisor
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input lo_is_125khz; // redundant signal, no longer used anywhere
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input [7:0] divisor;
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reg [7:0] to_arm_shiftreg;
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reg [7:0] pck_divider;
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reg ant_lo;
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// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
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// which is high for (divisor+1) pck0 cycles and low for the same duration
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// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
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// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
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always @(posedge pck0)
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begin
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if(pck_divider == divisor[7:0])
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begin
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pck_divider <= 8'd0;
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ant_lo = !ant_lo;
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end
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else
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begin
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pck_divider <= pck_divider + 1;
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end
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end
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// this task also runs at pck0 frequency (24Mhz) and is used to serialize
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// the ADC output which is then clocked into the ARM SSP.
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// because ant_lo always transitions when pck_divider = 0 we use the
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// pck_divider counter to sync our other signals off it
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// we read the ADC value when pck_divider=7 and shift it out on counts 8..15
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always @(posedge pck0)
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begin
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if((pck_divider == 8'd7) && !ant_lo)
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to_arm_shiftreg <= adc_d;
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else
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begin
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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// simulation showed a glitch occuring due to the LSB of the shifter
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// not being set as we shift bits out
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// this ensures the ssp_din remains low after a transfer and suppresses
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// the glitch that would occur when the last data shifted out ended in
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// a 1 bit and the next data shifted out started with a 0 bit
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to_arm_shiftreg[0] <= 1'b0;
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end
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end
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// ADC samples on falling edge of adc_clk, data available on the rising edge
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// example of ssp transfer of binary value 1100101
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// start of transfer is indicated by the rise of the ssp_frame signal
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// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
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// the ARM by the falling edge of ssp_clk
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// _______________________________
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// ssp_frame__| |__
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// _______ ___ ___
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// ssp_din __| |_______| |___| |______
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// _ _ _ _ _ _ _ _ _ _
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// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
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// serialized SSP data is gated by ant_lo to suppress unwanted signal
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assign ssp_din = to_arm_shiftreg[7] && !ant_lo;
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// SSP clock always runs at 24Mhz
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assign ssp_clk = pck0;
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// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
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assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;
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// unused signals tied low
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assign pwr_hi = 1'b0;
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assign pwr_oe1 = 1'b0;
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assign pwr_oe2 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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// this is the antenna driver signal
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assign pwr_lo = ant_lo;
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// ADC clock out of phase with antenna driver
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assign adc_clk = ~ant_lo;
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// ADC clock also routed to debug pin
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assign dbg = adc_clk;
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endmodule
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