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26 lines
742 B
Verilog
26 lines
742 B
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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module clk_divider(input clk, input [7:0] divisor, output [7:0] div_cnt, output div_clk);
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reg [7:0] div_cnt_ = 0;
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reg div_clk_;
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assign div_cnt = div_cnt_;
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assign div_clk = div_clk_;
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always @(posedge clk)
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begin
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if(div_cnt == divisor) begin
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div_cnt_ <= 8'd0;
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div_clk_ = !div_clk_;
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end else
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div_cnt_ <= div_cnt_ + 1;
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end
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endmodule
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