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101 lines
2.1 KiB
Verilog
101 lines
2.1 KiB
Verilog
`include "lo_read.v"
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/*
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pck0 - input main 24Mhz clock (PLL / 4)
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[7:0] adc_d - input data from A/D converter
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lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
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pwr_lo - output to coil drivers (ssp_clk / 8)
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adc_clk - output A/D clock signal
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ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
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ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
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ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
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ck_1356meg - input unused
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ck_1356megb - input unused
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ssp_dout - input unused
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cross_hi - input unused
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cross_lo - input unused
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pwr_hi - output unused, tied low
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pwr_oe1 - output unused, undefined
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pwr_oe2 - output unused, undefined
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pwr_oe3 - output unused, undefined
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pwr_oe4 - output unused, undefined
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dbg - output alias for adc_clk
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*/
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module testbed_lo_read;
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reg pck0;
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reg [7:0] adc_d;
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reg lo_is_125khz;
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reg [15:0] divisor;
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wire pwr_lo;
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wire adc_clk;
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wire ck_1356meg;
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wire ck_1356megb;
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wire ssp_frame;
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wire ssp_din;
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wire ssp_clk;
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reg ssp_dout;
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wire pwr_hi;
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wire pwr_oe1;
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wire pwr_oe2;
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wire pwr_oe3;
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wire pwr_oe4;
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wire cross_lo;
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wire cross_hi;
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wire dbg;
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lo_read #(5,10) dut(
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.pck0(pck0),
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.ck_1356meg(ck_1356meg),
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.ck_1356megb(ck_1356megb),
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.pwr_lo(pwr_lo),
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.pwr_hi(pwr_hi),
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.pwr_oe1(pwr_oe1),
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.pwr_oe2(pwr_oe2),
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.pwr_oe3(pwr_oe3),
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.pwr_oe4(pwr_oe4),
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.adc_d(adc_d),
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.adc_clk(adc_clk),
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.ssp_frame(ssp_frame),
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.ssp_din(ssp_din),
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.ssp_dout(ssp_dout),
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.ssp_clk(ssp_clk),
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.cross_hi(cross_hi),
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.cross_lo(cross_lo),
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.dbg(dbg),
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.lo_is_125khz(lo_is_125khz),
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.divisor(divisor)
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);
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integer idx, i, adc_val=8;
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// main clock
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always #5 pck0 = !pck0;
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task crank_dut;
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begin
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@(posedge adc_clk) ;
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adc_d = adc_val;
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adc_val = (adc_val *2) + 53;
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end
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endtask
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initial begin
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// init inputs
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pck0 = 0;
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adc_d = 0;
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ssp_dout = 0;
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lo_is_125khz = 1;
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divisor = 255; //min 16, 95=125Khz, max 255
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// simulate 4 A/D cycles at 125Khz
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for (i = 0 ; i < 8 ; i = i + 1) begin
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crank_dut;
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end
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$finish;
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end
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endmodule // main
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