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109 lines
3.9 KiB
Verilog
109 lines
3.9 KiB
Verilog
//-----------------------------------------------------------------------------
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// Pretend to be an ISO 14443 tag. We will do this by alternately short-
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// circuiting and open-circuiting the antenna coil, with the tri-state
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// pins.
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//
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// We communicate over the SSP, as a bitstream (i.e., might as well be
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// unframed, though we still generate the word sync signal). The output
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// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
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// -> ARM) is us using the A/D as a fancy comparator; this is with
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// (software-added) hysteresis, to undo the high-pass filter.
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//
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// At this point only Type A is implemented. This means that we are using a
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// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
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// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
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//
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// Jonathan Westhues, October 2006
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//-----------------------------------------------------------------------------
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module hi_simulate(
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pck0, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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cross_hi, cross_lo,
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dbg,
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mod_type
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);
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input pck0, ck_1356meg, ck_1356megb;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input [2:0] mod_type;
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// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
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// always be low.
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assign pwr_hi = 1'b0;
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assign pwr_lo = 1'b0;
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// The comparator with hysteresis on the output from the peak detector.
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reg after_hysteresis;
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assign adc_clk = ck_1356meg;
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always @(negedge adc_clk)
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begin
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if(& adc_d[7:5]) after_hysteresis = 1'b1;
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else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
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end
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// Divide 13.56 MHz by 32 to produce the SSP_CLK
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// The register is bigger to allow higher division factors of up to /128
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reg [6:0] ssp_clk_divider;
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always @(posedge adc_clk)
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ssp_clk_divider <= (ssp_clk_divider + 1);
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assign ssp_clk = ssp_clk_divider[4];
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// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
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// this is arbitrary, because it's just a bitstream.
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// One nasty issue, though: I can't make it work with both rx and tx at
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// once. The phase wrt ssp_clk must be changed. TODO to find out why
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// that is and make a better fix.
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reg [2:0] ssp_frame_divider_to_arm;
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always @(posedge ssp_clk)
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ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
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reg [2:0] ssp_frame_divider_from_arm;
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always @(negedge ssp_clk)
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ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
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reg ssp_frame;
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always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
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if(mod_type == 3'b000) // not modulating, so listening, to ARM
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ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
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else
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ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
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// Synchronize up the after-hysteresis signal, to produce DIN.
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reg ssp_din;
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always @(posedge ssp_clk)
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ssp_din = after_hysteresis;
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// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
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reg modulating_carrier;
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always @(mod_type or ssp_clk or ssp_dout)
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if(mod_type == 3'b000)
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modulating_carrier <= 1'b0; // no modulation
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else if(mod_type == 3'b001)
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modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
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else if(mod_type == 3'b010)
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modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
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else
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modulating_carrier <= 1'b0; // yet unused
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// This one is all LF, so doesn't matter
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assign pwr_oe2 = modulating_carrier;
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// Toggle only one of these, since we are already producing much deeper
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// modulation than a real tag would.
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assign pwr_oe1 = modulating_carrier;
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assign pwr_oe4 = modulating_carrier;
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// This one is always on, so that we can watch the carrier.
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assign pwr_oe3 = 1'b0;
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assign dbg = after_hysteresis;
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endmodule
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