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6658905f18
It is identical to the popular 20081211, with the doob addition (20090301), a linux client, and two additional commands for LF analysis. Let me know if you find issues here!
50 lines
963 B
Verilog
50 lines
963 B
Verilog
`include "fpga.v"
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module testbed_fpga;
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reg spck, mosi, ncs;
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wire miso;
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reg pck0i, ck_1356meg, ck_1356megb;
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wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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reg [7:0] adc_d;
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wire adc_clk, adc_noe;
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reg ssp_dout;
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wire ssp_frame, ssp_din, ssp_clk;
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fpga dut(
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spck, miso, mosi, ncs,
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pck0i, ck_1356meg, ck_1356megb,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk, adc_noe,
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ssp_frame, ssp_din, ssp_dout, ssp_clk
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);
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integer i;
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initial begin
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// init inputs
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#5 ncs=1;
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#5 spck = 1;
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#5 mosi = 1;
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#50 ncs=0;
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for (i = 0 ; i < 8 ; i = i + 1) begin
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#5 mosi = $random;
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#5 spck = 0;
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#5 spck = 1;
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end
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#5 ncs=1;
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#50 ncs=0;
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for (i = 0 ; i < 8 ; i = i + 1) begin
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#5 mosi = $random;
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#5 spck = 0;
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#5 spck = 1;
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end
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#5 ncs=1;
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#50 mosi=1;
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$finish;
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end
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endmodule // main
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