mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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439 lines
15 KiB
Coq
439 lines
15 KiB
Coq
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//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//-----------------------------------------------------------------------------
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/*
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Once upon a time the FPGA had a 16 input mux so we could have all LF and HF modules enabled and selectable
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As the functionality grew, we run out of space in the FPGA and we had to split into an "LF only" and an "HF only" FPGA bitstream
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But even then after a while it was not possible to fit all the HF functions at the same time so now we have multiple "HF only" bitstreams
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For example "Felica but without ISO14443", or "ISO14443 but without Felica" or "HF_15 but without Felica and ISO14443"
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Because of all of the above, you can not enable both HF and LF modes at the same time, because some LF modules outputs
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map to the same mux inputs as some HF modules outputs (thanks to reducing the mux from 16 to 8 inputs) and you can not have
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multiple outputs connected together therefore leading to a failed compilation
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*/
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// These defines are meant to be passed by the Makefile so do not uncomment them here
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// Proxmark3 RDV4 target
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//`define PM3RDV4
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// Proxmark3 generic target
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//`define PM3GENERIC
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// iCopy-X with XC3S100E
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//`define PM3ICOPYX
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// Pass desired defines to compiler to enable required modules
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// WITH_LF enables Low Frequency mode when defined else HF is enabled
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//`define WITH_LF
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// WITH_LF0 enables module reader
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//`define WITH_LF0
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// WITH_LF1 enables module edge detect
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//`define WITH_LF1
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// WITH_LF2 enables module passthrough
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//`define WITH_LF2
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// WITH_LF3 enables module ADC
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//`define WITH_LF3
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// WITH_HF0 enables module HF reader
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//`define WITH_HF0
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// WITH_HF1 enables module simulated tag
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//`define WITH_HF1
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// WITH_HF2 enables module ISO14443-A
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//`define WITH_HF2
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// WITH_HF3 enables module sniff
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//`define WITH_HF3
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// WITH_HF4 enables module ISO18092 FeliCa
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//`define WITH_HF4
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// WITH_HF5 enables module get trace
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//`define WITH_HF5
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//`include "define.v"
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//`include "util.v"
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//
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//`ifdef WITH_LF `include "clk_divider.v" `endif
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//`ifdef WITH_LF0 `include "lo_read.v" `endif
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//`ifdef WITH_LF1 `include "lo_edge_detect.v" `endif
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//`ifdef WITH_LF2 `include "lo_passthru.v" `endif
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//`ifdef WITH_LF3 `include "lo_adc.v" `endif
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//
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//`ifdef WITH_HF_15
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//`ifdef WITH_HF0 `include "hi_reader_15.v" `endif
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//`else
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//`ifdef WITH_HF0 `include "hi_reader.v" `endif
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//`endif
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//`ifdef WITH_HF1 `include "hi_simulate.v" `endif
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//`ifdef WITH_HF2 `include "hi_iso14443a.v" `endif
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//`ifdef WITH_HF3 `include "hi_sniffer.v" `endif
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//`ifdef WITH_HF4 `include "hi_flite.v" `endif
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//`ifdef WITH_HF5 `include "hi_get_trace.v" `endif
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module fpga_top(
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input ck_1356meg,
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input ck_1356megb,
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input spck,
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input pck0,
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input ncs,
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input [7:0] adc_d,
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input cross_hi,
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input cross_lo,
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input mosi,
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input ssp_dout,
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output ssp_din,
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output ssp_frame,
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output ssp_clk,
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output adc_clk,
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output adc_noe,
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output miso,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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output dbg
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);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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// Receive 16bits of data from ARM here.
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reg [15:0] shift_reg;
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always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
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reg trace_enable;
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reg [7:0] lf_ed_threshold;
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// adjustable frequency clock
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wire [7:0] pck_cnt;
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wire pck_divclk;
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reg [7:0] divisor;
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clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
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`ifdef WITH_LF
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reg [11:0] conf_word;
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`else
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reg [8:0] conf_word;
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`endif
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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// 4 bit command
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case (shift_reg[15:12])
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`ifdef WITH_LF
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`FPGA_CMD_SET_CONFREG:
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begin
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// 12 bit data
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conf_word <= shift_reg[11:0];
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if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT) lf_ed_threshold <= 127; // default threshold
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end
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`FPGA_CMD_SET_DIVISOR:
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divisor <= shift_reg[7:0]; // 8bits
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`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
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lf_ed_threshold <= shift_reg[7:0]; // 8 bits
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`else
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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`endif
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endcase
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end
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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// ############################################################################
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// # Enable Low Frequency Modules
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`ifdef WITH_LF
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// LF reader (generic)
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`ifdef WITH_LF0
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lo_read lr(
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.pck0 (pck0),
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.pck_divclk (pck_divclk),
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.pck_cnt (pck_cnt),
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.adc_d (adc_d),
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.lf_field (conf_word[0]),
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.ssp_din (mux0_ssp_din),
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.ssp_frame (mux0_ssp_frame),
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.ssp_clk (mux0_ssp_clk),
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.adc_clk (mux0_adc_clk),
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.pwr_lo (mux0_pwr_lo),
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.pwr_hi (mux0_pwr_hi),
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.pwr_oe1 (mux0_pwr_oe1),
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.pwr_oe2 (mux0_pwr_oe2),
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.pwr_oe3 (mux0_pwr_oe3),
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.pwr_oe4 (mux0_pwr_oe4),
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.debug (mux0_debug)
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);
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`endif
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// LF edge detect (generic)
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`ifdef WITH_LF1
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lo_edge_detect le(
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.pck0 (pck0),
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.pck_divclk (pck_divclk),
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.adc_d (adc_d),
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.cross_lo (cross_lo),
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.lf_field (conf_word[0]),
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.lf_ed_toggle_mode (conf_word[1]),
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.lf_ed_threshold (lf_ed_threshold),
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.ssp_dout (ssp_dout),
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.ssp_frame (mux1_ssp_frame),
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.ssp_clk (mux1_ssp_clk),
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.adc_clk (mux1_adc_clk),
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.pwr_lo (mux1_pwr_lo),
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.pwr_hi (mux1_pwr_hi),
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.pwr_oe1 (mux1_pwr_oe1),
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.pwr_oe2 (mux1_pwr_oe2),
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.pwr_oe3 (mux1_pwr_oe3),
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.pwr_oe4 (mux1_pwr_oe4),
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.debug (mux1_debug)
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);
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`endif
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// LF passthrough
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`ifdef WITH_LF2
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lo_passthru lp(
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.pck_divclk (pck_divclk),
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.cross_lo (cross_lo),
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.ssp_dout (ssp_dout),
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.ssp_din (mux2_ssp_din),
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.adc_clk (mux2_adc_clk),
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.pwr_lo (mux2_pwr_lo),
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.pwr_hi (mux2_pwr_hi),
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.pwr_oe1 (mux2_pwr_oe1),
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.pwr_oe2 (mux2_pwr_oe2),
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.pwr_oe3 (mux2_pwr_oe3),
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.pwr_oe4 (mux2_pwr_oe4),
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.debug (mux2_debug)
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);
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`endif
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// LF ADC (read/write)
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`ifdef WITH_LF3
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lo_adc la(
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.pck0 (pck0),
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.adc_d (adc_d),
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.divisor (divisor),
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.lf_field (conf_word[0]),
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.ssp_dout (ssp_dout),
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.ssp_din (mux3_ssp_din),
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.ssp_frame (mux3_ssp_frame),
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.ssp_clk (mux3_ssp_clk),
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.adc_clk (mux3_adc_clk),
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.pwr_lo (mux3_pwr_lo ),
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.pwr_hi (mux3_pwr_hi ),
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.pwr_oe1 (mux3_pwr_oe1),
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.pwr_oe2 (mux3_pwr_oe2),
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.pwr_oe3 (mux3_pwr_oe3),
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.pwr_oe4 (mux3_pwr_oe4),
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.debug (mux3_debug)
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);
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`endif // WITH_LF3
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assign mux6_pwr_lo = 1'b1;
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// 7 -- SPARE
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`else // if WITH_LF not defined
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// ############################################################################
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// # Enable High Frequency Modules
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// HF reader
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`ifdef WITH_HF0
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`ifdef WITH_HF_15
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hi_reader_15 hr(
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`else
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hi_reader hr(
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`endif
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.ck_1356meg (ck_1356megb),
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.adc_d (adc_d),
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.subcarrier_frequency (conf_word[5:4]),
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.minor_mode (conf_word[3:0]),
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.ssp_dout (ssp_dout),
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.ssp_din (mux0_ssp_din),
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.ssp_frame (mux0_ssp_frame),
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.ssp_clk (mux0_ssp_clk),
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.adc_clk (mux0_adc_clk),
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.pwr_lo (mux0_pwr_lo),
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.pwr_hi (mux0_pwr_hi),
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.pwr_oe1 (mux0_pwr_oe1),
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.pwr_oe2 (mux0_pwr_oe2),
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.pwr_oe3 (mux0_pwr_oe3),
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.pwr_oe4 (mux0_pwr_oe4),
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.debug (mux0_debug)
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);
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`endif // WITH_HF0
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// HF simulated tag
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`ifdef WITH_HF1
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hi_simulate hs(
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.ck_1356meg (ck_1356meg),
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.adc_d (adc_d),
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.mod_type (conf_word[3:0]),
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.ssp_dout (ssp_dout),
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.ssp_din (mux1_ssp_din),
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.ssp_frame (mux1_ssp_frame),
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.ssp_clk (mux1_ssp_clk),
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.adc_clk (mux1_adc_clk),
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.pwr_lo (mux1_pwr_lo),
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.pwr_hi (mux1_pwr_hi),
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.pwr_oe1 (mux1_pwr_oe1),
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.pwr_oe2 (mux1_pwr_oe2),
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.pwr_oe3 (mux1_pwr_oe3),
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.pwr_oe4 (mux1_pwr_oe4),
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.debug (mux1_debug)
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);
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`endif // WITH_HF1
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// HF ISO14443-A
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`ifdef WITH_HF2
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hi_iso14443a hisn(
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.ck_1356meg (ck_1356meg),
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.adc_d (adc_d),
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.mod_type (conf_word[3:0]),
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.ssp_dout (ssp_dout),
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.ssp_din (mux2_ssp_din),
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.ssp_frame (mux2_ssp_frame),
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.ssp_clk (mux2_ssp_clk),
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.adc_clk (mux2_adc_clk),
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.pwr_lo (mux2_pwr_lo),
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.pwr_hi (mux2_pwr_hi),
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.pwr_oe1 (mux2_pwr_oe1),
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.pwr_oe2 (mux2_pwr_oe2),
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.pwr_oe3 (mux2_pwr_oe3),
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.pwr_oe4 (mux2_pwr_oe4),
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.debug (mux2_debug)
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);
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`endif // WITH_HF2
|
||
|
|
|
||
|
|
// HF sniff
|
||
|
|
`ifdef WITH_HF3
|
||
|
|
hi_sniffer he(
|
||
|
|
.ck_1356meg (ck_1356megb),
|
||
|
|
.adc_d (adc_d),
|
||
|
|
|
||
|
|
.ssp_din (mux3_ssp_din),
|
||
|
|
.ssp_frame (mux3_ssp_frame),
|
||
|
|
.ssp_clk (mux3_ssp_clk),
|
||
|
|
.adc_clk (mux3_adc_clk),
|
||
|
|
.pwr_lo (mux3_pwr_lo),
|
||
|
|
.pwr_hi (mux3_pwr_hi),
|
||
|
|
.pwr_oe1 (mux3_pwr_oe1),
|
||
|
|
.pwr_oe2 (mux3_pwr_oe2),
|
||
|
|
.pwr_oe3 (mux3_pwr_oe3),
|
||
|
|
.pwr_oe4 (mux3_pwr_oe4)
|
||
|
|
);
|
||
|
|
`endif //WITH_HF3
|
||
|
|
|
||
|
|
// HF ISO18092 FeliCa
|
||
|
|
`ifdef WITH_HF4
|
||
|
|
hi_flite hfl(
|
||
|
|
.ck_1356meg (ck_1356megb),
|
||
|
|
.adc_d (adc_d),
|
||
|
|
.mod_type (conf_word[3:0]),
|
||
|
|
.ssp_dout (ssp_dout),
|
||
|
|
|
||
|
|
.ssp_din (mux4_ssp_din),
|
||
|
|
.ssp_frame (mux4_ssp_frame),
|
||
|
|
.ssp_clk (mux4_ssp_clk),
|
||
|
|
.adc_clk (mux4_adc_clk),
|
||
|
|
.pwr_lo (mux4_pwr_lo),
|
||
|
|
.pwr_hi (mux4_pwr_hi),
|
||
|
|
.pwr_oe1 (mux4_pwr_oe1),
|
||
|
|
.pwr_oe2 (mux4_pwr_oe2),
|
||
|
|
.pwr_oe3 (mux4_pwr_oe3),
|
||
|
|
.pwr_oe4 (mux4_pwr_oe4),
|
||
|
|
.debug (mux4_debug)
|
||
|
|
);
|
||
|
|
`endif // WITH_HF4
|
||
|
|
|
||
|
|
// HF get trace
|
||
|
|
`ifdef WITH_HF5
|
||
|
|
hi_get_trace gt(
|
||
|
|
.ck_1356megb (ck_1356megb),
|
||
|
|
.adc_d (adc_d),
|
||
|
|
.trace_enable (trace_enable),
|
||
|
|
.major_mode (conf_word[8:6]),
|
||
|
|
.ssp_din (mux5_ssp_din),
|
||
|
|
.ssp_frame (mux5_ssp_frame),
|
||
|
|
.ssp_clk (mux5_ssp_clk)
|
||
|
|
);
|
||
|
|
`endif // WITH_HF5
|
||
|
|
|
||
|
|
`endif // WITH_LF
|
||
|
|
|
||
|
|
// These assignments must agree with the defines in fpgaloader.h
|
||
|
|
// Major modes Low Frequency
|
||
|
|
// mux0 = LF reader (generic)
|
||
|
|
// mux1 = LF edge detect (generic)
|
||
|
|
// mux2 = LF passthrough
|
||
|
|
// mux3 = LF ADC (read/write)
|
||
|
|
// mux4 = SPARE
|
||
|
|
// mux5 = SPARE
|
||
|
|
// mux6 = SPARE
|
||
|
|
// mux7 = FPGA_MAJOR_MODE_OFF
|
||
|
|
|
||
|
|
// Major modes High Frequency
|
||
|
|
// mux0 = HF reader
|
||
|
|
// mux1 = HF simulated tag
|
||
|
|
// mux2 = HF ISO14443-A
|
||
|
|
// mux3 = HF sniff
|
||
|
|
// mux4 = HF ISO18092 FeliCa
|
||
|
|
// mux5 = HF get trace
|
||
|
|
// mux6 = unused
|
||
|
|
// mux7 = FPGA_MAJOR_MODE_OFF
|
||
|
|
|
||
|
|
mux8 mux_ssp_clk (.sel(conf_word[8:6]), .y(ssp_clk ), .x0(mux0_ssp_clk ), .x1(mux1_ssp_clk ), .x2(mux2_ssp_clk ), .x3(mux3_ssp_clk ), .x4(mux4_ssp_clk ), .x5(mux5_ssp_clk ), .x6(mux6_ssp_clk ), .x7(mux7_ssp_clk ) );
|
||
|
|
mux8 mux_ssp_din (.sel(conf_word[8:6]), .y(ssp_din ), .x0(mux0_ssp_din ), .x1(mux1_ssp_din ), .x2(mux2_ssp_din ), .x3(mux3_ssp_din ), .x4(mux4_ssp_din ), .x5(mux5_ssp_din ), .x6(mux6_ssp_din ), .x7(mux7_ssp_din ) );
|
||
|
|
mux8 mux_ssp_frame (.sel(conf_word[8:6]), .y(ssp_frame), .x0(mux0_ssp_frame), .x1(mux1_ssp_frame), .x2(mux2_ssp_frame), .x3(mux3_ssp_frame), .x4(mux4_ssp_frame), .x5(mux5_ssp_frame), .x6(mux6_ssp_frame), .x7(mux7_ssp_frame) );
|
||
|
|
mux8 mux_pwr_oe1 (.sel(conf_word[8:6]), .y(pwr_oe1 ), .x0(mux0_pwr_oe1 ), .x1(mux1_pwr_oe1 ), .x2(mux2_pwr_oe1 ), .x3(mux3_pwr_oe1 ), .x4(mux4_pwr_oe1 ), .x5(mux5_pwr_oe1 ), .x6(mux6_pwr_oe1 ), .x7(mux7_pwr_oe1 ) );
|
||
|
|
mux8 mux_pwr_oe2 (.sel(conf_word[8:6]), .y(pwr_oe2 ), .x0(mux0_pwr_oe2 ), .x1(mux1_pwr_oe2 ), .x2(mux2_pwr_oe2 ), .x3(mux3_pwr_oe2 ), .x4(mux4_pwr_oe2 ), .x5(mux5_pwr_oe2 ), .x6(mux6_pwr_oe2 ), .x7(mux7_pwr_oe2 ) );
|
||
|
|
mux8 mux_pwr_oe3 (.sel(conf_word[8:6]), .y(pwr_oe3 ), .x0(mux0_pwr_oe3 ), .x1(mux1_pwr_oe3 ), .x2(mux2_pwr_oe3 ), .x3(mux3_pwr_oe3 ), .x4(mux4_pwr_oe3 ), .x5(mux5_pwr_oe3 ), .x6(mux6_pwr_oe3 ), .x7(mux7_pwr_oe3 ) );
|
||
|
|
mux8 mux_pwr_oe4 (.sel(conf_word[8:6]), .y(pwr_oe4 ), .x0(mux0_pwr_oe4 ), .x1(mux1_pwr_oe4 ), .x2(mux2_pwr_oe4 ), .x3(mux3_pwr_oe4 ), .x4(mux4_pwr_oe4 ), .x5(mux5_pwr_oe4 ), .x6(mux6_pwr_oe4 ), .x7(mux7_pwr_oe4 ) );
|
||
|
|
mux8 mux_pwr_lo (.sel(conf_word[8:6]), .y(pwr_lo ), .x0(mux0_pwr_lo ), .x1(mux1_pwr_lo ), .x2(mux2_pwr_lo ), .x3(mux3_pwr_lo ), .x4(mux4_pwr_lo ), .x5(mux5_pwr_lo ), .x6(mux6_pwr_lo ), .x7(mux7_pwr_lo ) );
|
||
|
|
mux8 mux_pwr_hi (.sel(conf_word[8:6]), .y(pwr_hi ), .x0(mux0_pwr_hi ), .x1(mux1_pwr_hi ), .x2(mux2_pwr_hi ), .x3(mux3_pwr_hi ), .x4(mux4_pwr_hi ), .x5(mux5_pwr_hi ), .x6(mux6_pwr_hi ), .x7(mux7_pwr_hi ) );
|
||
|
|
mux8 mux_adc_clk (.sel(conf_word[8:6]), .y(adc_clk ), .x0(mux0_adc_clk ), .x1(mux1_adc_clk ), .x2(mux2_adc_clk ), .x3(mux3_adc_clk ), .x4(mux4_adc_clk ), .x5(mux5_adc_clk ), .x6(mux6_adc_clk ), .x7(mux7_adc_clk ) );
|
||
|
|
mux8 mux_dbg (.sel(conf_word[8:6]), .y(dbg ), .x0(mux0_debug ), .x1(mux1_debug ), .x2(mux2_debug ), .x3(mux3_debug ), .x4(mux4_debug ), .x5(mux5_debug ), .x6(mux6_debug ), .x7(mux7_debug ) );
|
||
|
|
|
||
|
|
endmodule
|