mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-11-14 21:58:44 +08:00
480 lines
20 KiB
Tcl
480 lines
20 KiB
Tcl
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#
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# Project automation script for fpga_hf
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#
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# Created for ISE version 10.1
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#
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# This file contains several Tcl procedures (procs) that you can use to automate
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# your project by running from xtclsh or the Project Navigator Tcl console.
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# If you load this file (using the Tcl command: source fpga_hf.tcl, then you can
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# run any of the procs included here.
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# You may also edit any of these procs to customize them. See comments in each
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# proc for more instructions.
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#
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# This file contains the following procedures:
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#
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# Top Level procs (meant to be called directly by the user):
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# run_process: you can use this top-level procedure to run any processes
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# that you choose to by adding and removing comments, or by
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# adding new entries.
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# rebuild_project: you can alternatively use this top-level procedure
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# to recreate your entire project, and the run selected processes.
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#
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# Lower Level (helper) procs (called under in various cases by the top level procs):
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# show_help: print some basic information describing how this script works
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# add_source_files: adds the listed source files to your project.
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# set_project_props: sets the project properties that were in effect when this
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# script was generated.
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# create_libraries: creates and adds file to VHDL libraries that were defined when
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# this script was generated.
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# create_partitions: adds any partitions that were defined when this script was generated.
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# set_process_props: set the process properties as they were set for your project
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# when this script was generated.
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#
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set myProject "fpga_hf.ise"
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set myScript "fpga_hf.tcl"
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#
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# Main (top-level) routines
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#
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#
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# run_process
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# This procedure is used to run processes on an existing project. You may comment or
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# uncomment lines to control which processes are run. This routine is set up to run
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# the Implement Design and Generate Programming File processes by default. This proc
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# also sets process properties as specified in the "set_process_props" proc. Only
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# those properties which have values different from their current settings in the project
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# file will be modified in the project.
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#
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proc run_process {} {
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global myScript
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global myProject
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## put out a 'heartbeat' - so we know something's happening.
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puts "\n$myScript: running ($myProject)...\n"
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if { ! [ open_project ] } {
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return false
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}
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set_process_props
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#
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# Remove the comment characters (#'s) to enable the following commands
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# process run "Synthesize"
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# process run "Translate"
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# process run "Map"
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# process run "Place & Route"
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#
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puts "Running 'Implement Design'"
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if { ! [ process run "Implement Design" ] } {
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puts "$myScript: Implementation run failed, check run output for details."
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project close
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return
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}
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puts "Running 'Generate Programming File'"
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if { ! [ process run "Generate Programming File" ] } {
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puts "$myScript: Generate Programming File run failed, check run output for details."
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project close
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return
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}
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puts "Run completed."
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project close
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}
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#
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# rebuild_project
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#
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# This procedure renames the project file (if it exists) and recreates the project.
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# It then sets project properties and adds project sources as specified by the
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# set_project_props and add_source_files support procs. It recreates VHDL libraries
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# and partitions as they existed at the time this script was generated.
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#
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# It then calls run_process to set process properties and run selected processes.
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#
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proc rebuild_project {} {
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global myScript
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global myProject
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## put out a 'heartbeat' - so we know something's happening.
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puts "\n$myScript: rebuilding ($myProject)...\n"
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if { [ file exists $myProject ] } {
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puts "$myScript: Removing existing project file."
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file delete $myProject
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}
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puts "$myScript: Rebuilding project $myProject"
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project new $myProject
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set_project_props
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add_source_files
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create_libraries
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create_partitions
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puts "$myScript: project rebuild completed."
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run_process
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}
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#
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# Support Routines
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#
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#
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# show_help: print information to help users understand the options available when
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# running this script.
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#
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proc show_help {} {
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global myScript
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puts ""
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puts "usage: xtclsh $myScript <options>"
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puts " or you can run xtclsh and then enter 'source $myScript'."
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puts ""
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puts "options:"
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puts " run_process - set properties and run processes."
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puts " rebuild_project - rebuild the project from scratch and run processes."
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puts " set_project_props - set project properties (device, speed, etc.)"
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puts " add_source_files - add source files"
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puts " create_libraries - create vhdl libraries"
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puts " create_partitions - create partitions"
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puts " set_process_props - set process property values"
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puts " show_help - print this message"
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puts ""
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}
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proc open_project {} {
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global myScript
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global myProject
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if { ! [ file exists $myProject ] } {
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## project file isn't there, rebuild it.
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puts "Project $myProject not found. Use ${myProject}_rebuild to recreate it."
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return false
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}
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project open $myProject
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return true
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}
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#
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# set_project_props
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#
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# This procedure sets the project properties as they were set in the project
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# at the time this script was generated.
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#
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proc set_project_props {} {
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global myScript
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if { ! [ open_project ] } {
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return false
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}
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puts "$myScript: Setting project properties..."
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project set family "Spartan3E"
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project set device "xc3s100e"
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project set package "vq100"
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project set speed "-4"
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project set top_level_module_type "HDL"
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project set synthesis_tool "XST (VHDL/Verilog)"
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project set simulator "ISE Simulator (VHDL/Verilog)"
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project set "Preferred Language" "Verilog"
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project set "Enable Message Filtering" "false"
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project set "Display Incremental Messages" "false"
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}
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#
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# add_source_files
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#
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# This procedure add the source files that were known to the project at the
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# time this script was generated.
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#
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proc add_source_files {} {
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global myScript
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if { ! [ open_project ] } {
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return false
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}
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puts "$myScript: Adding sources to project..."
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xfile add "../../clk_divider.v"
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xfile add "../../define.v"
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xfile add "../../fpga.ucf"
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xfile add "../../fpga_allinone.v"
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xfile add "../../fpga_hfmod.v"
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xfile add "../../fpga_lfmod.v"
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xfile add "../../hi_flite.v"
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xfile add "../../hi_get_trace.v"
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xfile add "../../hi_iso14443a.v"
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xfile add "../../hi_reader.v"
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xfile add "../../hi_simulate.v"
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xfile add "../../hi_sniffer.v"
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xfile add "../../lf_edge_detect.v"
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xfile add "../../lo_adc.v"
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xfile add "../../lo_edge_detect.v"
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xfile add "../../lo_passthru.v"
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xfile add "../../lo_read.v"
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xfile add "../../lp20khz_1MSa_iir_filter.v"
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xfile add "../../mux2_onein.v"
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xfile add "../../mux2_oneout.v"
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xfile add "../../util.v"
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# Set the Top Module as well...
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project set top "fpga_hf"
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puts "$myScript: project sources reloaded."
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} ; # end add_source_files
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#
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# create_libraries
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#
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# This procedure defines VHDL libraries and associates files with those libraries.
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# It is expected to be used when recreating the project. Any libraries defined
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# when this script was generated are recreated by this procedure.
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#
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proc create_libraries {} {
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global myScript
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if { ! [ open_project ] } {
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return false
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}
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puts "$myScript: Creating libraries..."
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# must close the project or library definitions aren't saved.
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project close
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} ; # end create_libraries
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#
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# create_partitions
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#
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# This procedure creates partitions on instances in your project.
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# It is expected to be used when recreating the project. Any partitions
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# defined when this script was generated are recreated by this procedure.
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#
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proc create_partitions {} {
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global myScript
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if { ! [ open_project ] } {
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return false
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}
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puts "$myScript: Creating Partitions..."
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# must close the project or partition definitions aren't saved.
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project close
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} ; # end create_partitions
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#
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# set_process_props
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#
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# This procedure sets properties as requested during script generation (either
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# all of the properties, or only those modified from their defaults).
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#
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proc set_process_props {} {
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global myScript
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if { ! [ open_project ] } {
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return false
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}
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puts "$myScript: setting process properties..."
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project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
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project set "Use SmartGuide" "false"
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project set "SmartGuide Filename" "fpga_hf_guide.ncd"
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project set "Multiplier Style" "Auto" -process "Synthesize - XST"
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project set "Configuration Rate" "Default (1)" -process "Generate Programming File"
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project set "Map to Input Functions" "4" -process "Map"
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project set "Number of Clock Buffers" "24" -process "Synthesize - XST"
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project set "Max Fanout" "500" -process "Synthesize - XST"
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project set "Case Implementation Style" "None" -process "Synthesize - XST"
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project set "Decoder Extraction" "true" -process "Synthesize - XST"
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project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST"
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project set "Mux Extraction" "Yes" -process "Synthesize - XST"
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project set "RAM Extraction" "true" -process "Synthesize - XST"
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project set "ROM Extraction" "true" -process "Synthesize - XST"
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project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
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project set "Logical Shifter Extraction" "true" -process "Synthesize - XST"
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project set "Optimization Goal" "Speed" -process "Synthesize - XST"
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project set "Optimization Effort" "Normal" -process "Synthesize - XST"
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project set "Resource Sharing" "true" -process "Synthesize - XST"
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project set "Shift Register Extraction" "true" -process "Synthesize - XST"
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project set "XOR Collapsing" "true" -process "Synthesize - XST"
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project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
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project set "Show All Models" "false" -process "Generate IBIS Model"
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project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
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project set "Ignore User Timing Constraints" "false" -process "Map"
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project set "Use RLOC Constraints" "true" -process "Map"
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project set "Other Map Command Line Options" "" -process "Map"
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project set "Use LOC Constraints" "true" -process "Translate"
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project set "Other Ngdbuild Command Line Options" "" -process "Translate"
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project set "Ignore User Timing Constraints" "false" -process "Place & Route"
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project set "Other Place & Route Command Line Options" "" -process "Place & Route"
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project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
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project set "Reset DCM if SHUTDOWN & AGHIGH performed" "false" -process "Generate Programming File"
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project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
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project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
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project set "Create Binary Configuration File" "false" -process "Generate Programming File"
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project set "Create Bit File" "true" -process "Generate Programming File"
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project set "Enable BitStream Compression" "false" -process "Generate Programming File"
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project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
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project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
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project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
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project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
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project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
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project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
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project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
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project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
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project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
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project set "Drive Done Pin High" "false" -process "Generate Programming File"
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project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
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project set "Release DLL (Output Events)" "Default (NoWait)" -process "Generate Programming File"
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project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
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project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
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project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
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project set "Optimization Strategy (Cover Mode)" "Area" -process "Map"
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project set "Disable Register Ordering" "false" -process "Map"
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project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
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project set "Replicate Logic to Allow Logic Level Reduction" "true" -process "Map"
|
||
|
|
project set "Generate Detailed MAP Report" "false" -process "Map"
|
||
|
|
project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
|
||
|
|
project set "Perform Timing-Driven Packing and Placement" "false" -process "Map"
|
||
|
|
project set "Trim Unconnected Signals" "true" -process "Map"
|
||
|
|
project set "Create I/O Pads from Ports" "false" -process "Translate"
|
||
|
|
project set "Macro Search Path" "" -process "Translate"
|
||
|
|
project set "Netlist Translation Type" "Timestamp" -process "Translate"
|
||
|
|
project set "User Rules File for Netlister Launcher" "" -process "Translate"
|
||
|
|
project set "Allow Unexpanded Blocks" "false" -process "Translate"
|
||
|
|
project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
|
||
|
|
project set "Starting Placer Cost Table (1-100)" "1" -process "Place & Route"
|
||
|
|
project set "Placer Effort Level (Overrides Overall Level)" "None" -process "Place & Route"
|
||
|
|
project set "Router Effort Level (Overrides Overall Level)" "None" -process "Place & Route"
|
||
|
|
project set "Place And Route Mode" "Normal Place and Route" -process "Place & Route"
|
||
|
|
project set "Use Bonded I/Os" "false" -process "Place & Route"
|
||
|
|
project set "Add I/O Buffers" "true" -process "Synthesize - XST"
|
||
|
|
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
|
||
|
|
project set "Keep Hierarchy" "No" -process "Synthesize - XST"
|
||
|
|
project set "Register Balancing" "No" -process "Synthesize - XST"
|
||
|
|
project set "Register Duplication" "true" -process "Synthesize - XST"
|
||
|
|
project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
|
||
|
|
project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
|
||
|
|
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
|
||
|
|
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
|
||
|
|
project set "Case" "Maintain" -process "Synthesize - XST"
|
||
|
|
project set "Cores Search Directories" "" -process "Synthesize - XST"
|
||
|
|
project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
|
||
|
|
project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
|
||
|
|
project set "FSM Style" "LUT" -process "Synthesize - XST"
|
||
|
|
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
|
||
|
|
project set "Generics, Parameters" "" -process "Synthesize - XST"
|
||
|
|
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
|
||
|
|
project set "HDL INI File" "" -process "Synthesize - XST"
|
||
|
|
project set "Library Search Order" "" -process "Synthesize - XST"
|
||
|
|
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
|
||
|
|
project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
|
||
|
|
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
|
||
|
|
project set "Read Cores" "true" -process "Synthesize - XST"
|
||
|
|
project set "Slice Packing" "true" -process "Synthesize - XST"
|
||
|
|
project set "Slice Utilization Ratio" "100" -process "Synthesize - XST"
|
||
|
|
project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
|
||
|
|
project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
|
||
|
|
project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
|
||
|
|
project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
|
||
|
|
project set "Custom Compile File List" "" -process "Synthesize - XST"
|
||
|
|
project set "Verilog Include Directories" "" -process "Synthesize - XST"
|
||
|
|
project set "Verilog 2001" "true" -process "Synthesize - XST"
|
||
|
|
project set "Verilog Macros" "" -process "Synthesize - XST"
|
||
|
|
project set "Work Directory" "./xst" -process "Synthesize - XST"
|
||
|
|
project set "Write Timing Constraints" "false" -process "Synthesize - XST"
|
||
|
|
project set "Other XST Command Line Options" "" -process "Synthesize - XST"
|
||
|
|
project set "Map Effort Level" "Medium" -process "Map"
|
||
|
|
project set "Combinatorial Logic Optimization" "false" -process "Map"
|
||
|
|
project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
|
||
|
|
project set "Power Reduction" "false" -process "Map"
|
||
|
|
project set "Register Duplication" "false" -process "Map"
|
||
|
|
project set "Synthesis Constraints File" "" -process "Synthesize - XST"
|
||
|
|
project set "Mux Style" "Auto" -process "Synthesize - XST"
|
||
|
|
project set "RAM Style" "Auto" -process "Synthesize - XST"
|
||
|
|
project set "Timing Mode" "Non Timing Driven" -process "Map"
|
||
|
|
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
|
||
|
|
project set "Generate Clock Region Report" "false" -process "Place & Route"
|
||
|
|
project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
|
||
|
|
project set "Generate Post-Place & Route Static Timing Report" "true" -process "Place & Route"
|
||
|
|
project set "Nodelist File (Unix Only)" "" -process "Place & Route"
|
||
|
|
project set "Number of PAR Iterations (0-100)" "3" -process "Place & Route"
|
||
|
|
project set "Save Results in Directory (.dir will be appended)" "" -process "Place & Route"
|
||
|
|
project set "Number of Results to Save (0-100)" "" -process "Place & Route"
|
||
|
|
project set "Power Reduction" "false" -process "Place & Route"
|
||
|
|
project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
|
||
|
|
project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
|
||
|
|
project set "CLB Pack Factor Percentage" "100" -process "Map"
|
||
|
|
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
|
||
|
|
project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
|
||
|
|
project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
|
||
|
|
project set "ROM Style" "Auto" -process "Synthesize - XST"
|
||
|
|
project set "Safe Implementation" "No" -process "Synthesize - XST"
|
||
|
|
project set "Extra Effort" "None" -process "Map"
|
||
|
|
project set "Power Activity File" "" -process "Map"
|
||
|
|
project set "Power Activity File" "" -process "Place & Route"
|
||
|
|
project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
|
||
|
|
|
||
|
|
puts "$myScript: project property values set."
|
||
|
|
|
||
|
|
} ; # end set_process_props
|
||
|
|
|
||
|
|
proc main {} {
|
||
|
|
|
||
|
|
if { [llength $::argv] == 0 } {
|
||
|
|
show_help
|
||
|
|
return true
|
||
|
|
}
|
||
|
|
|
||
|
|
foreach option $::argv {
|
||
|
|
switch $option {
|
||
|
|
"show_help" { show_help }
|
||
|
|
"run_process" { run_process }
|
||
|
|
"rebuild_project" { rebuild_project }
|
||
|
|
"set_project_props" { set_project_props }
|
||
|
|
"add_source_files" { add_source_files }
|
||
|
|
"create_libraries" { create_libraries }
|
||
|
|
"create_partitions" { create_partitions }
|
||
|
|
"set_process_props" { set_process_props }
|
||
|
|
default { puts "unrecognized option: $option"; show_help }
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if { $tcl_interactive } {
|
||
|
|
show_help
|
||
|
|
} else {
|
||
|
|
if {[catch {main} result]} {
|
||
|
|
puts "$myScript failed: $result."
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|