RfidResearchGroup/proxmark3
1
1
Fork 0
mirror of https://github.com/RfidResearchGroup/proxmark3.git synced 2024-09-20 15:26:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #219 from drandreas/master

Browse source 
WIP: Clean Legic Reader
This commit is contained in:
Iceman 2018-08-06 14:55:08 +02:00 committed by GitHub
parent 7d0fd7203e 058426fa17
commit 0df3a49ecc
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
5 changed files with 404 additions and 1643 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
armsrc/fpgaloader.h
View file

@ -74,6 +74,7 @@ extern void switch_off(void);
// Options for the HF reader, correlating against rx from tag
#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
#define FPGA_HF_READER_RX_XCORR_QUARTER (1<<2)
// Options for the HF simulated tag, how to modulate
#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) // 0000
#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) // 0001

1994
armsrc/legicrf.c
View file

File diff suppressed because it is too large Load diff

35
armsrc/legicrf.h
View file

@ -11,38 +11,11 @@
#ifndef __LEGICRF_H
#define __LEGICRF_H
#include "proxmark3.h" //
#include "apps.h"
#include "util.h" //
#include "string.h"
#include "legic_prng.h" // legic PRNG impl
#include "crc.h" // legic crc-4
#include "ticks.h" // timers
#include "legic.h" // legic_card_select_t struct
#include "proxmark3.h"
extern void LegicRfSimulate(int phase, int frame, int reqresp);
extern int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv);
extern void LegicRfWriter(uint16_t offset, uint16_t byte, uint8_t iv, uint8_t *data);
extern void LegicRfInfo(void);
uint32_t get_key_stream(int skip, int count);
void frame_send_tag(uint16_t response, uint8_t bits);
void frame_sendAsReader(uint32_t data, uint8_t bits);
int legic_read_byte( uint16_t index, uint8_t cmd_sz);
bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz);
int legic_select_card(legic_card_select_t *p_card);
int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv);
void LegicCommonInit(bool clear_mem);
// emulator mem
void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data);
void LegicEMemGet(uint32_t arg0, uint32_t arg1);
void legic_emlset_mem(uint8_t *data, int offset, int numofbytes);
void legic_emlget_mem(uint8_t *data, int offset, int numofbytes);
void ice_legic_setup();
extern void LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv);
extern void LegicRfWriter(uint16_t offset, uint16_t byte, uint8_t iv, uint8_t *data);
extern void LegicRfSimulate(int phase, int frame, int reqresp);
#endif /* __LEGICRF_H */

BIN
fpga/fpga_hf.bit
View file

Binary file not shown.

17
fpga/hi_read_tx.v
View file

@ -71,19 +71,8 @@ always @(negedge ssp_clk)
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
assign ssp_din = 1'b0;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[6:4]) after_hysteresis <= 1'b1;
else if(~(| adc_d[6:4])) after_hysteresis <= 1'b0;
end
assign dbg = ssp_frame;
assign ssp_din = after_hysteresis;
assign dbg = after_hysteresis;
endmodule
endmodule