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https://github.com/RfidResearchGroup/proxmark3.git
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Add command and code for bidirectional LF emulation of Hitag2. Should be extended for other types of tags
This commit is contained in:
henryk@ploetzli.ch
parent
802a36162a
commit
0fa9ca5b53
6 changed files with 215 additions and 2 deletions
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@ -14,6 +14,7 @@ THUMBSRC = start.c \
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iso15693.c \
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util.c \
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version.c \
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hitag2.c \
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usb.c
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# These are to be compiled in ARM mode
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@ -645,6 +645,9 @@ void UsbPacketReceived(BYTE *packet, int len)
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case CMD_VERSION:
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SendVersion();
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break;
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case CMD_LF_SIMULATE_BIDIR:
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SimulateTagLowFrequencyBidir(c->ext1, c->ext2);
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break;
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#ifdef WITH_LCD
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case CMD_LCD_RESET:
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LCDReset();
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@ -74,6 +74,7 @@ void AcquireRawBitsTI(void);
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void SimulateTagLowFrequency(int period, int ledcontrol);
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void CmdHIDsimTAG(int hi, int lo, int ledcontrol);
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void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol);
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void SimulateTagLowFrequencyBidir(int divisor, int max_bitlen);
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/// iso14443.h
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void SimulateIso14443Tag(void);
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201
armsrc/lfops.c
201
armsrc/lfops.c
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@ -6,6 +6,7 @@
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//-----------------------------------------------------------------------------
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#include <proxmark3.h>
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#include "apps.h"
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#include "hitag2.h"
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#include "../common/crc16.c"
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void AcquireRawAdcSamples125k(BOOL at134khz)
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@ -61,6 +62,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
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{
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BOOL at134khz;
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/* Make sure the tag is reset */
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelay(2500);
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// see if 'h' was specified
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if(command[strlen((char *) command) - 1] == 'h')
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at134khz= TRUE;
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@ -77,6 +82,8 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
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// Give it a bit of time for the resonant antenna to settle.
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SpinDelay(50);
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// And a little more time for the tag to fully power up
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SpinDelay(2000);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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@ -95,11 +102,12 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
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}
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LED_D_ON();
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if(*(command++) == '0')
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if(*(command++) == '0') {
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SpinDelayUs(period_0);
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else
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} else {
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SpinDelayUs(period_1);
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}
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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SpinDelayUs(delay_off);
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@ -478,6 +486,195 @@ void SimulateTagLowFrequency(int period, int ledcontrol)
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}
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}
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/* Provides a framework for bidirectional LF tag communication
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* Encoding is currently Hitag2, but the general idea can probably
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* be transferred to other encodings.
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*
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* The new FPGA code will, for the LF simulator mode, give on SSC_FRAME
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* (PA15) a thresholded version of the signal from the ADC. Setting the
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* ADC path to the low frequency peak detection signal, will enable a
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* somewhat reasonable receiver for modulation on the carrier signal
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* that is generated by the reader. The signal is low when the reader
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* field is switched off, and high when the reader field is active. Due
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* to the way that the signal looks like, mostly only the rising edge is
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* useful, your mileage may vary.
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*
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* Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also
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* TIOA1, which can be used as the capture input for timer 1. This should
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* make it possible to measure the exact edge-to-edge time, without processor
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* intervention.
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*
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* Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)
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* t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)
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*
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* The following defines are in carrier periods:
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*/
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#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
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#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */
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#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
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#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */
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static void hitag_handle_frame(int t0, int frame_len, char *frame);
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//#define DEBUG_RA_VALUES 1
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#define DEBUG_FRAME_CONTENTS 1
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void SimulateTagLowFrequencyBidir(int divisor, int t0)
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{
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#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS
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int i = 0;
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#endif
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char frame[10];
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int frame_pos=0;
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DbpString("Starting Hitag2 emulator, press button to end");
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hitag2_init();
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/* Set up simulator mode, frequency divisor which will drive the FPGA
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* and analog mux selection.
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*/
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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RELAY_OFF();
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/* Set up Timer 1:
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* Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
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* external trigger rising edge, load RA on rising edge of TIOA, load RB on rising
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* edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
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*/
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PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);
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PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);
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TC1_CCR = TC_CCR_CLKDIS;
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TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |
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TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;
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TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
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/* calculate the new value for the carrier period in terms of TC1 values */
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t0 = t0/2;
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int overflow = 0;
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while(!BUTTON_PRESS()) {
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WDT_HIT();
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if(TC1_SR & TC_SR_LDRAS) {
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int ra = TC1_RA;
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if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;
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#if DEBUG_RA_VALUES
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if(ra > 255 || overflow) ra = 255;
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((char*)BigBuf)[i] = ra;
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i = (i+1) % 8000;
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#endif
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if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {
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/* Ignore */
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} else if(ra >= t0*HITAG_T_1_MIN ) {
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/* '1' bit */
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if(frame_pos < 8*sizeof(frame)) {
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frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );
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frame_pos++;
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}
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} else if(ra >= t0*HITAG_T_0_MIN) {
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/* '0' bit */
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if(frame_pos < 8*sizeof(frame)) {
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frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );
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frame_pos++;
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}
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}
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overflow = 0;
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LED_D_ON();
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} else {
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if(TC1_CV > t0*HITAG_T_EOF) {
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/* Minor nuisance: In Capture mode, the timer can not be
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* stopped by a Compare C. There's no way to stop the clock
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* in software, so we'll just have to note the fact that an
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* overflow happened and the next loaded timer value might
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* have wrapped. Also, this marks the end of frame, and the
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* still running counter can be used to determine the correct
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* time for the start of the reply.
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*/
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overflow = 1;
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if(frame_pos > 0) {
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/* Have a frame, do something with it */
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#if DEBUG_FRAME_CONTENTS
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((char*)BigBuf)[i++] = frame_pos;
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memcpy( ((char*)BigBuf)+i, frame, 7);
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i+=7;
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i = i % sizeof(BigBuf);
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#endif
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hitag_handle_frame(t0, frame_pos, frame);
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memset(frame, 0, sizeof(frame));
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}
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frame_pos = 0;
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}
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LED_D_OFF();
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}
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}
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DbpString("All done");
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}
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static void hitag_send_bit(int t0, int bit) {
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if(bit == 1) {
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/* Manchester: Loaded, then unloaded */
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LED_A_ON();
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SHORT_COIL();
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while(TC1_CV < t0*15);
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OPEN_COIL();
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while(TC1_CV < t0*31);
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LED_A_OFF();
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} else if(bit == 0) {
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/* Manchester: Unloaded, then loaded */
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LED_B_ON();
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OPEN_COIL();
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while(TC1_CV < t0*15);
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SHORT_COIL();
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while(TC1_CV < t0*31);
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LED_B_OFF();
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}
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TC1_CCR = TC_CCR_SWTRG; /* Reset clock for the next bit */
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}
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static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)
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{
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OPEN_COIL();
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PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);
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/* Wait for HITAG_T_WRESP carrier periods after the last reader bit,
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* not that since the clock counts since the rising edge, but T_wresp is
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* with respect to the falling edge, we need to wait actually (T_wresp - T_g)
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* periods. The gap time T_g varies (4..10).
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*/
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while(TC1_CV < t0*(fdt-8));
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int saved_cmr = TC1_CMR;
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TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */
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TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */
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int i;
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for(i=0; i<5; i++)
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hitag_send_bit(t0, 1); /* Start of frame */
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for(i=0; i<frame_len; i++) {
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hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );
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}
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OPEN_COIL();
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TC1_CMR = saved_cmr;
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}
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/* Callback structure to cleanly separate tag emulation code from the radio layer. */
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static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)
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{
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hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);
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return 0;
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}
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/* Frame length in bits, frame contents in MSBit first format */
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static void hitag_handle_frame(int t0, int frame_len, char *frame)
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{
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hitag2_handle_command(frame, frame_len, hitag_cb, &t0);
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}
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// compose fc/8 fc/10 waveform
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static void fc(int c, int *n) {
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BYTE *dest = (BYTE *)BigBuf;
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@ -50,6 +50,7 @@ typedef struct {
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#define CMD_HID_DEMOD_FSK 0x020B
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#define CMD_HID_SIM_TAG 0x020C
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#define CMD_SET_LF_DIVISOR 0x020D
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#define CMD_LF_SIMULATE_BIDIR 0x020E
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// For the 13.56 MHz tags
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#define CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693 0x0300
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@ -663,6 +663,15 @@ static void CmdLosim(char *str)
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SendCommand(&c, FALSE);
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}
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static void CmdLosimBidir(char *str)
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{
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UsbCommand c;
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c.cmd = CMD_LF_SIMULATE_BIDIR;
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c.ext1 = 47; /* Set ADC to twice the carrier for a slight supersampling */
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c.ext2 = 384;
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SendCommand(&c, FALSE);
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}
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static void CmdLoread(char *str)
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{
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UsbCommand c;
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@ -2834,6 +2843,7 @@ static struct {
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{"loread", CmdLoread, 0, "['h'] -- Read 125/134 kHz LF ID-only tag (option 'h' for 134)"},
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{"losamples", CmdLosamples, 0, "[128 - 16000] -- Get raw samples for LF tag"},
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{"losim", CmdLosim, 0, "Simulate LF tag"},
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{"losimbidir", CmdLosimBidir, 0, "Simulate LF tag (with bidirectional data transmission between reader and tag)"},
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{"ltrim", CmdLtrim, 1, "<samples> -- Trim samples from left of trace"},
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{"mandemod", Cmdmanchesterdemod, 1, "[i] [clock rate] -- Manchester demodulate binary stream (option 'i' to invert output)"},
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{"manmod", Cmdmanchestermod, 1, "[clock rate] -- Manchester modulate a binary stream"},
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