After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4. Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug

CHANGELOG.md

@@ -3,6 +3,7 @@ All notable changes to this project will be documented in this file.
 This project uses the changelog in accordance with [keepchangelog](http://keepachangelog.com/). Please use this to write notable changes, which is not the same as git commit log...
 
 ## [unreleased][unreleased]
+ - Swapped to OE1 for Shallow modulation on RDV4. Thanks to @gentlekiwi for testing (@d18c7db)
  - Changed iClass SIO and Legacy credential detection to be more reliable (@nvx)
  - Added `hf iclass esetblk` - set iClass emulator memory block data (@nvx)
  - Added cryptorf regressiontests (@iceman1001)

armsrc/fpgaloader.h

@@ -105,6 +105,7 @@ thres|                          x x x x x x x x
 #define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE         (6<<0)
 #define FPGA_HF_READER_MODE_SNIFF_PHASE             (7<<0)
 #define FPGA_HF_READER_MODE_SEND_JAM                (8<<0)
+#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4   (9<<0)
 
 #define FPGA_HF_READER_SUBCARRIER_848_KHZ           (0<<4)
 #define FPGA_HF_READER_SUBCARRIER_424_KHZ           (1<<4)

armsrc/iso14443b.c

@@ -1407,7 +1407,11 @@ static void TransmitFor14443b_AsReader(uint32_t *start_time) {
 
     tosend_t *ts = get_tosend();
 
+#ifdef RDV4
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4);
+#else 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD);
+#endif    
 
     // TR2 minimum 14 ETUs
     if (*start_time < ISO14B_TR0) {
@@ -2102,7 +2106,12 @@ void iso14443b_setup(void) {
     FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER);
 
     // Signal field is on with the appropriate LED
+#ifdef RDV4
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4);
+#else 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_SHALLOW_MOD);
+#endif    
+
     SpinDelay(100);
 
     // Start the timer

armsrc/iso15693.c

@@ -294,7 +294,12 @@ void CodeIso15693AsTag(const uint8_t *cmd, size_t len) {
 // Transmit the command (to the tag) that was placed in cmd[].
 void TransmitTo15693Tag(const uint8_t *cmd, int len, uint32_t *start_time, bool shallow_mod) {
 
+#ifdef RDV4
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | (shallow_mod ? FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4 : FPGA_HF_READER_MODE_SEND_FULL_MOD));
+#else 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | (shallow_mod ? FPGA_HF_READER_MODE_SEND_SHALLOW_MOD : FPGA_HF_READER_MODE_SEND_FULL_MOD));
+#endif    
+
 
     if (*start_time < DELAY_ARM_TO_TAG) {
         *start_time = DELAY_ARM_TO_TAG;

fpga/define.v

@@ -129,6 +129,7 @@
 `define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE         6
 `define FPGA_HF_READER_MODE_SNIFF_PHASE             7
 `define FPGA_HF_READER_MODE_SEND_JAM                8
+`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4   9
 
 `define FPGA_HF_READER_SUBCARRIER_848_KHZ           0
 `define FPGA_HF_READER_SUBCARRIER_424_KHZ           1

fpga/hi_reader.v

@@ -28,7 +28,7 @@ module hi_reader(
     output adc_clk,
     output pwr_lo,
     output reg pwr_hi,
-    output pwr_oe1,
+    output reg pwr_oe1,
     output pwr_oe2,
     output pwr_oe3,
     output reg pwr_oe4,
@@ -412,6 +412,11 @@ begin
         pwr_hi  = ck_1356meg;
         pwr_oe4 = ssp_dout;
     end
+    else if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD_RDV4)
+    begin
+        pwr_hi  = ck_1356meg;
+        pwr_oe1 = ssp_dout;
+    end
     else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
     begin
         pwr_hi  = ck_1356meg & ~ssp_dout;
@@ -437,7 +442,7 @@ begin
 end
 
 // always on
-assign pwr_oe1 = 1'b0;
+// assign pwr_oe1 = 1'b0;
 assign pwr_oe3 = 1'b0;
 
 // Unused.