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Updated logic in lo_read.v so it's much tidier now, better timing.
Commented source and recompiled FPGA to new fpgaimg.c
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armsrc/fpgaimg.c
15218
armsrc/fpgaimg.c
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@ -1,8 +1,7 @@
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//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency read mode. In this case
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// we are generating the 134 kHz or 125 kHz carrier, and running the
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// unmodulated carrier at that frequency. The A/D samples at that same rate,
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// and the result is serialized.
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// we are generating the unmodulated low frequency carrier.
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// The A/D samples at that same rate and the result is serialized.
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//
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// Jonathan Westhues, April 2006
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//-----------------------------------------------------------------------------
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@ -24,54 +23,81 @@ module lo_read(
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output ssp_frame, ssp_din, ssp_clk;
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input cross_hi, cross_lo;
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output dbg;
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input lo_is_125khz;
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input lo_is_125khz; // redundant signal, no longer used anywhere
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input [7:0] divisor;
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// The low-frequency RFID stuff. This is relatively simple, because most
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// of the work happens on the ARM, and we just pass samples through. The
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// PCK0 must be divided down to generate the A/D clock, and from there by
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// a factor of 8 to generate the carrier (that we apply to the coil drivers).
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//
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// This is also where we decode the received synchronous serial port words,
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// to determine how to drive the output enables.
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// PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do
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// 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by
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// dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).
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reg [7:0] to_arm_shiftreg;
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reg [7:0] pck_divider;
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reg [6:0] ssp_divider;
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reg ant_lo;
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// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
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// which is high for (divisor+1) pck0 cycles and low for the same duration
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// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
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// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
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always @(posedge pck0)
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begin
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if(pck_divider == 8'd0)
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if(pck_divider == divisor[7:0])
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begin
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pck_divider <= divisor[7:0];
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pck_divider <= 8'd0;
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ant_lo = !ant_lo;
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if(ant_lo == 1'b0)
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begin
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ssp_divider <= 7'b0011111;
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to_arm_shiftreg <= adc_d;
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end
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end
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else
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begin
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pck_divider <= pck_divider - 1;
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if(ssp_divider[6] == 1'b0)
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begin
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if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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ssp_divider <= ssp_divider - 1;
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end
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pck_divider <= pck_divider + 1;
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end
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end
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assign ssp_din = to_arm_shiftreg[7];
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assign ssp_clk = pck_divider[1];
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assign ssp_frame = ~ssp_divider[5];
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// this task also runs at pck0 frequency (24Mhz) and is used to serialize
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// the ADC output which is then clocked into the ARM SSP.
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// because ant_lo always transitions when pck_divider = 0 we use the
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// pck_divider counter to sync our other signals off it
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// we read the ADC value when pck_divider=7 and shift it out on counts 8..15
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always @(posedge pck0)
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begin
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if((pck_divider == 8'd7) && !ant_lo)
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to_arm_shiftreg <= adc_d;
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else
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begin
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to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
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// simulation showed a glitch occuring due to the LSB of the shifter
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// not being set as we shift bits out
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// this ensures the ssp_din remains low after a transfer and suppresses
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// the glitch that would occur when the last data shifted out ended in
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// a 1 bit and the next data shifted out started with a 0 bit
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to_arm_shiftreg[0] <= 1'b0;
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end
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end
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// ADC samples on falling edge of adc_clk, data available on the rising edge
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// example of ssp transfer of binary value 1100101
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// start of transfer is indicated by the rise of the ssp_frame signal
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// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
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// the ARM by the falling edge of ssp_clk
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// _______________________________
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// ssp_frame__| |__
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// _______ ___ ___
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// ssp_din __| |_______| |___| |______
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// _ _ _ _ _ _ _ _ _ _
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// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
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// serialized SSP data is gated by ant_lo to suppress unwanted signal
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assign ssp_din = to_arm_shiftreg[7] && !ant_lo;
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// SSP clock always runs at 24Mhz
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assign ssp_clk = pck0;
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// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
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assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;
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// unused signals tied low
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assign pwr_hi = 1'b0;
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assign pwr_oe1 = 1'b0;
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assign pwr_oe2 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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// this is the antenna driver signal
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assign pwr_lo = ant_lo;
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// ADC clock out of phase with antenna driver
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assign adc_clk = ~ant_lo;
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// ADC clock also routed to debug pin
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assign dbg = adc_clk;
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endmodule
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@ -1,4 +1,3 @@
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`include "lo_read_org.v"
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`include "lo_read.v"
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/*
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pck0 - input main 24Mhz clock (PLL / 4)
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@ -38,7 +37,7 @@ module testbed_lo_read;
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wire ssp_frame;
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wire ssp_din;
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wire ssp_clk;
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wire ssp_dout;
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reg ssp_dout;
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wire pwr_hi;
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wire pwr_oe1;
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wire pwr_oe2;
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@ -48,47 +47,25 @@ module testbed_lo_read;
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wire cross_hi;
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wire dbg;
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lo_read_org #(5,10) dut1(
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lo_read #(5,10) dut(
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.pck0(pck0),
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.ck_1356meg(ack_1356meg),
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.ck_1356megb(ack_1356megb),
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.pwr_lo(apwr_lo),
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.pwr_hi(apwr_hi),
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.pwr_oe1(apwr_oe1),
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.pwr_oe2(apwr_oe2),
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.pwr_oe3(apwr_oe3),
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.pwr_oe4(apwr_oe4),
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.ck_1356meg(ck_1356meg),
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.ck_1356megb(ck_1356megb),
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.pwr_lo(pwr_lo),
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.pwr_hi(pwr_hi),
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.pwr_oe1(pwr_oe1),
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.pwr_oe2(pwr_oe2),
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.pwr_oe3(pwr_oe3),
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.pwr_oe4(pwr_oe4),
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.adc_d(adc_d),
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.adc_clk(adc_clk),
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.ssp_frame(assp_frame),
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.ssp_din(assp_din),
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.ssp_dout(assp_dout),
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.ssp_clk(assp_clk),
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.cross_hi(across_hi),
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.cross_lo(across_lo),
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.dbg(adbg),
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.lo_is_125khz(lo_is_125khz)
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);
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lo_read #(5,10) dut2(
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.pck0(pck0),
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.ck_1356meg(bck_1356meg),
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.ck_1356megb(bck_1356megb),
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.pwr_lo(bpwr_lo),
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.pwr_hi(bpwr_hi),
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.pwr_oe1(bpwr_oe1),
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.pwr_oe2(bpwr_oe2),
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.pwr_oe3(bpwr_oe3),
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.pwr_oe4(bpwr_oe4),
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.adc_d(adc_d),
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.adc_clk(badc_clk),
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.ssp_frame(bssp_frame),
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.ssp_din(bssp_din),
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.ssp_dout(bssp_dout),
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.ssp_clk(bssp_clk),
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.cross_hi(bcross_hi),
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.cross_lo(bcross_lo),
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.dbg(bdbg),
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.ssp_frame(ssp_frame),
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.ssp_din(ssp_din),
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.ssp_dout(ssp_dout),
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.ssp_clk(ssp_clk),
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.cross_hi(cross_hi),
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.cross_lo(cross_lo),
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.dbg(dbg),
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.lo_is_125khz(lo_is_125khz),
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.divisor(divisor)
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);
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@ -111,8 +88,9 @@ module testbed_lo_read;
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// init inputs
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pck0 = 0;
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adc_d = 0;
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ssp_dout = 0;
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lo_is_125khz = 1;
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divisor=255; //min 19, 95=125Khz, max 255
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divisor = 255; //min 16, 95=125Khz, max 255
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// simulate 4 A/D cycles at 125Khz
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for (i = 0 ; i < 8 ; i = i + 1) begin
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