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Shorten threshold registers to number of used bits

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This commit is contained in:
Christian Zietz 2024-02-03 11:44:18 +01:00
parent 404d0a8c7b
commit 225bb420c6
6 changed files with 4 additions and 4 deletions
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fpga/fpga_icopyx_hf.bit
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fpga/fpga_pm3_felica.bit
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fpga/fpga_pm3_hf.bit
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fpga/fpga_pm3_hf_15.bit
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fpga/fpga_pm3_lf.bit
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fpga/fpga_pm3_top.v
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@ -111,8 +111,8 @@ always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
reg trace_enable;
reg [7:0] lf_ed_threshold;
reg [10:0] hf_edge_detect_threshold;
reg [10:0] hf_edge_detect_threshold_high;
reg [5:0] hf_edge_detect_threshold;
reg [5:0] hf_edge_detect_threshold_high;
// adjustable frequency clock
wire [7:0] pck_cnt;
@ -157,8 +157,8 @@ begin
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
begin
hf_edge_detect_threshold <= {6'b0, shift_reg[5:0]};
hf_edge_detect_threshold_high <= {6'b0, shift_reg[11:6]};
hf_edge_detect_threshold <= shift_reg[5:0];
hf_edge_detect_threshold_high <= shift_reg[11:6];
end
`endif
endcase