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Make Style and remove some comments.

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Thomas Sutter 2019-10-17 13:48:34 +02:00
parent 97f85ba50a
commit 376e367d45
4 changed files with 49 additions and 49 deletions
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8
armsrc/felica.c
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@ -14,17 +14,17 @@
// FeliCa timings // FeliCa timings
// minimum time between the start bits of consecutive transfers from reader to tag: 6800 carrier (13.56MHz) cycles // minimum time between the start bits of consecutive transfers from reader to tag: 6800 carrier (13.56MHz) cycles
#ifndef FELICA_REQUEST_GUARD_TIME #ifndef FELICA_REQUEST_GUARD_TIME
# define FELICA_REQUEST_GUARD_TIME (6800/16 + 1) // 426 # define FELICA_REQUEST_GUARD_TIME (6800/16 + 1)
#endif #endif
// FRAME DELAY TIME 2672 carrier cycles // FRAME DELAY TIME 2672 carrier cycles
#ifndef FELICA_FRAME_DELAY_TIME #ifndef FELICA_FRAME_DELAY_TIME
# define FELICA_FRAME_DELAY_TIME (2672/16 + 1) // 168 # define FELICA_FRAME_DELAY_TIME (2672/16 + 1)
#endif #endif
#ifndef DELAY_AIR2ARM_AS_READER #ifndef DELAY_AIR2ARM_AS_READER
#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16) // 27 + 128 + 64 - 128 = 91 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
#endif #endif
#ifndef DELAY_ARM2AIR_AS_READER #ifndef DELAY_ARM2AIR_AS_READER
#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1) // 64 + 128 + 17 = 209 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
#endif #endif
// CRC skips two first sync bits in data buffer // CRC skips two first sync bits in data buffer