mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-03-17 18:50:32 +08:00
prepare to update the LF T55XX commands
This commit is contained in:
parent
a8d4906ba5
commit
385f398740
6 changed files with 110 additions and 94 deletions
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@ -20,6 +20,7 @@
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#include <strings.h>
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#include "../common/crc32.h"
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#include "BigBuf.h"
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#include "../include/hitag2.h"
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extern const uint8_t OddByteParity[256];
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extern int rsamples; // = 0;
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@ -116,9 +117,9 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc);
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void AcquireTiType(void);
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void AcquireRawBitsTI(void);
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void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol);
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void SimulateTagLowFrequencyA(int period, int gap);
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//void SimulateTagLowFrequencyA(int period, int gap);
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void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol);
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void CmdHIDsimTAG(int hi, int lo, int ledcontrol);
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void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol);
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void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol);
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void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol);
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@ -15,6 +15,7 @@
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#include "epa.h"
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#include "../common/cmd.h"
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// Protocol and Parameter Selection Request
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// use regular (1x) speed in both directions
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// CRC is already included
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@ -13,6 +13,7 @@
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#ifndef __ISO14443A_H
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#define __ISO14443A_H
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#include "../include/common.h"
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#include "../include/mifare.h"
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#include "mifaresniff.h"
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typedef struct {
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158
armsrc/lfops.c
158
armsrc/lfops.c
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@ -82,8 +82,10 @@ void LFSetupFPGAForADC(int divisor, bool lf_field)
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Give it a bit of time for the resonant antenna to settle.
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SpinDelay(50);
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SpinDelay(150);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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}
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@ -465,7 +467,7 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
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DbpString("Now use tiread to check");
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}
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void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
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void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
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{
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int i;
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uint8_t *tab = BigBuf_get_addr();
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@ -897,10 +899,20 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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* To compensate antenna falling times shorten the write times
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* and enlarge the gap ones.
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*/
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#define START_GAP 250
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#define WRITE_GAP 160
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#define WRITE_0 144 // 192
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#define WRITE_1 400 // 432 for T55x7; 448 for E5550
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#define START_GAP 30*8 // 10 - 50fc 250
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#define WRITE_GAP 20*8 // 8 - 30fc
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#define WRITE_0 24*8 // 16 - 31fc 24fc 192
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#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
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// VALUES TAKEN FROM EM4x function: SendForward
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// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
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// WRITE_GAP = 128; (16*8)
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// WRITE_1 = 256 32*8; (32*8)
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// These timings work for 4469/4269/4305 (with the 55*8 above)
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// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
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#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
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// Write one bit to card
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void T55xxWriteBit(int bit)
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@ -908,7 +920,7 @@ void T55xxWriteBit(int bit)
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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if (bit == 0)
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if (!bit)
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SpinDelayUs(WRITE_0);
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else
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SpinDelayUs(WRITE_1);
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@ -919,16 +931,11 @@ void T55xxWriteBit(int bit)
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// Write one card block in page 0, no lock
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void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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{
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//unsigned int i; //enio adjustment 12/10/14
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uint32_t i;
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uint32_t i = 0;
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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SpinDelay(150);
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// Set up FPGA, 125kHz
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// Wait for config.. (192+8190xPOW)x8 == 67ms
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LFSetupFPGAForADC(0, true);
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// Now start writting
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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@ -965,26 +972,15 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
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void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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{
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uint8_t *dest = BigBuf_get_addr();
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//int m=0, i=0; //enio adjustment 12/10/14
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uint32_t m=0, i=0;
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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m = BigBuf_max_traceLen();
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// Clear destination buffer before sending the command
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memset(dest, 128, m);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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LED_D_ON();
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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SpinDelay(150);
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// Now start writting
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//uint16_t bufferlength = BigBuf_max_traceLen();
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uint16_t bufferlength = T55xx_SAMPLES_SIZE;
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uint32_t i = 0;
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// Clear destination buffer before sending the command 0x80 = average.
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memset(dest, 0x80, bufferlength);
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// Set up FPGA, 125kHz
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// Wait for config.. (192+8190xPOW)x8 == 67ms
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LFSetupFPGAForADC(0, true);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayUs(START_GAP);
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@ -1003,53 +999,40 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
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T55xxWriteBit(Block & i);
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// Turn field on to read the response
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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TurnReadLFOn();
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// Now do the acquisition
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i = 0;
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for(;;) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
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AT91C_BASE_SSC->SSC_THR = 0x43;
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//AT91C_BASE_SSC->SSC_THR = 0xff;
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LED_D_ON();
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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// we don't care about actual value, only if it's more or less than a
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// threshold essentially we capture zero crossings for later analysis
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// if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
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i++;
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if (i >= m) break;
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++i;
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LED_D_OFF();
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if (i >= bufferlength) break;
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}
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}
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cmd_send(CMD_ACK,0,0,0,0,0);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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LED_D_OFF();
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DbpString("DONE!");
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}
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// Read card traceability data (page 1)
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void T55xxReadTrace(void){
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uint8_t *dest = BigBuf_get_addr();
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int m=0, i=0;
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//uint16_t bufferlength = BigBuf_max_traceLen();
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uint16_t bufferlength = T55xx_SAMPLES_SIZE;
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uint32_t i = 0;
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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m = BigBuf_max_traceLen();
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// Clear destination buffer before sending the command
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memset(dest, 128, m);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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LED_D_ON();
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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// And for the tag to fully power up
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SpinDelay(150);
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// Now start writting
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// Clear destination buffer before sending the command 0x80 = average
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memset(dest, 0x80, bufferlength);
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LFSetupFPGAForADC(0, true);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelayUs(START_GAP);
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@ -1058,25 +1041,34 @@ void T55xxReadTrace(void){
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T55xxWriteBit(1); //Page 1
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// Turn field on to read the response
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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TurnReadLFOn();
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// Now do the acquisition
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i = 0;
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for(;;) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
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AT91C_BASE_SSC->SSC_THR = 0x43;
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LED_D_ON();
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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if (i >= m) break;
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}
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}
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++i;
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LED_D_OFF();
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if (i >= bufferlength) break;
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}
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}
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cmd_send(CMD_ACK,0,0,0,0,0);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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LED_D_OFF();
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DbpString("DONE!");
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}
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void TurnReadLFOn(){
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Give it a bit of time for the resonant antenna to settle.
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//SpinDelay(30);
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SpinDelayUs(8*150);
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}
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/*-------------- Cloning routines -----------*/
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void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
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uint8_t *dest = BigBuf_get_addr();
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uint16_t bufferlength = BigBuf_max_traceLen();
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uint32_t i = 0;
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// Clear destination buffer before sending the command 0x80 = average.
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memset(dest, 0x80, bufferlength);
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uint8_t fwd_bit_count;
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uint8_t *dest = BigBuf_get_addr();
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int m=0, i=0;
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//If password mode do login
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if (PwdMode == 1) EM4xLogin(Pwd);
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@ -1811,9 +1808,6 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
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fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
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fwd_bit_count += Prepare_Addr( Address );
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m = BigBuf_max_traceLen();
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// Clear destination buffer before sending the command
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memset(dest, 128, m);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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}
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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i++;
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if (i >= m) break;
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}
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}
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++i;
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if (i >= bufferlength) break;
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}
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}
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cmd_send(CMD_ACK,0,0,0,0,0);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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LED_D_OFF();
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}
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@ -65,8 +65,12 @@ int CmdReadBlk(const char *Cmd)
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int invert = 0;
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int clk = 0;
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int block = -1;
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int errCnt;
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size_t bitlen;
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//int decodedBitlen;
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uint32_t blockData;
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uint8_t bits[MAX_GRAPH_TRACE_LEN] = {0x00};
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sscanf(Cmd, "%d", &block);
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if ((block > 7) | (block < 0)) {
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SendCommand(&c);
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if ( !WaitForResponseTimeout(CMD_ACK,NULL,1500) ) {
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PrintAndLog("command execution time out");
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return 1;
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return 2;
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}
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CmdSamples("");
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CmdSamples("12000");
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size_t bitlen = getFromGraphBuf(bits);
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bitlen = getFromGraphBuf(bits);
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int errCnt = askrawdemod(bits, &bitlen, &clk, &invert);
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errCnt = askrawdemod(bits, &bitlen, &clk, &invert);
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//throw away static - allow 1 and -1 (in case of threshold command first)
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if ( errCnt == -1 || bitlen < 16 ){
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PrintAndLog("no data found");
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if (g_debugMode)
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PrintAndLog("errCnt: %d, bitlen: %d, clk: %d, invert: %d", errCnt, bitlen, clk, invert);
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return 0;
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return 3;
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}
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if (g_debugMode)
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PrintAndLog("Using Clock: %d - invert: %d - Bits Found: %d", clk, invert, bitlen);
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//move bits back to DemodBuffer
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setDemodBuf(bits, bitlen, 0);
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printBitStream(bits,bitlen);
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// bits has the manchester encoded data.
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errCnt = manrawdecode(bits, &bitlen);
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if ( errCnt == -1 || bitlen < 16 ){
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PrintAndLog("no data found");
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if (g_debugMode)
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PrintAndLog("errCnt: %d, bitlen: %d, clk: %d, invert: %d", errCnt, bitlen, clk, invert);
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return 4;
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}
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blockData = PackBits(0, 32, bits);
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if ( block < 0)
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PrintAndLog(" Decoded : 0x%08X %s", blockData, sprint_bin(bits,32) );
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else
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PrintAndLog(" Block %d : 0x%08X %s", block, blockData, sprint_bin(bits,32) );
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return 0;
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}
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@ -391,9 +412,7 @@ int ManchesterDemod(int blockNum){
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uint8_t bits[LF_BITSSTREAM_LEN] = {0x00};
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uint8_t * bitstream = bits;
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//manchester_decode(GraphBuffer, LF_TRACE_BUFF_SIZE, bitstream, LF_BITSSTREAM_LEN);
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manchester_decode(GraphBuffer, LF_TRACE_BUFF_SIZE, bits, LF_BITSSTREAM_LEN);
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//blockData = PackBits(offset, sizebyte, bitstream);
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blockData = PackBits(offset, sizebyte, bits);
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if ( blockNum < 0)
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@ -524,7 +543,7 @@ static command_t CommandTable[] =
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{"trace", CmdReadTrace, 0, "[1] Read T55xx traceability data (page 1/ blk 0-1)"},
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{"info", CmdInfo, 0, "[1] Read T55xx configuration data (page 0/ blk 0)"},
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{"dump", CmdDump, 0, "[password] Dump T55xx card block 0-7. optional with password"},
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{"fsk", CmdIceFsk, 0, "FSK demod"},
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//{"fsk", CmdIceFsk, 0, "FSK demod"},
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{"man", CmdIceManchester, 0, "Manchester demod (with SST)"},
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{NULL, NULL, 0, NULL}
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};
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@ -213,8 +213,6 @@ int manchester_decode( int * data, const size_t len, uint8_t * dataout, size_t
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int ManchesterConvertFrom1(const int * data, const size_t len, uint8_t * dataout,int dataoutlen, int clock, int startIndex){
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PrintAndLog(" Path B");
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int i,j, bitindex, lc, tolerance, warnings;
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warnings = 0;
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int upperlimit = len*2/clock+8;
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