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CHG: @ikarus23 removed all missleadning warnings for GCC6.1.1.
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parent
62577a62ae
commit
3c6542087e
3 changed files with 16 additions and 21 deletions
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@ -49,8 +49,7 @@ static void ConfigClocks(void)
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PMC_MAIN_OSC_STARTUP_DELAY(8);
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// wait for main oscillator to stabilize
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
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;
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
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// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
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// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
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@ -63,8 +62,7 @@ static void ConfigClocks(void)
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PMC_PLL_USB_DIVISOR(1);
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// wait for PLL to lock
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
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;
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
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// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
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// datasheet recommends that this register is programmed in two operations
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@ -72,15 +70,13 @@ static void ConfigClocks(void)
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
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// wait for main clock ready signal
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
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;
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
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// set the source to PLL
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
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// wait for main clock ready signal
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
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;
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
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}
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static void Fatal(void) {
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@ -199,8 +195,7 @@ static void flash_mode(int externally_entered)
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size_t rx_len;
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usb_enable();
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for (volatile size_t i=0; i<0x100000; i++)
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;
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for (volatile size_t i=0; i<0x100000; i++) {};
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for(;;) {
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WDT_HIT();
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@ -655,14 +655,17 @@ int CmdHF14ACmdRaw(const char *cmd) {
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c.arg[2] = 13560000 / 1000 / (8*16) * timeout; // timeout in ETUs (time to transfer 1 bit, approx. 9.4 us)
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}
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if(power)
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if(power) {
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c.arg[0] |= ISO14A_NO_DISCONNECT;
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if(datalen>0)
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}
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if(datalen>0) {
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c.arg[0] |= ISO14A_RAW;
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if(topazmode)
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}
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if(topazmode) {
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c.arg[0] |= ISO14A_TOPAZMODE;
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}
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// Max buffer is USB_CMD_DATA_SIZE
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datalen = (datalen > USB_CMD_DATA_SIZE) ? USB_CMD_DATA_SIZE : datalen;
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@ -81,12 +81,9 @@ size_t removeParity(uint8_t *BitStream, size_t startIdx, uint8_t pLen, uint8_t p
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j--; // overwrite parity with next data
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// if parity fails then return 0
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switch (pType) {
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case 3: if (BitStream[j]==1) return 0; break; //should be 0 spacer bit
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case 2: if (BitStream[j]==0) return 0; break; //should be 1 spacer bit
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default: //test parity
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if (parityTest(parityWd, pLen, pType) == 0)
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return 0;
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break;
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case 3: if (BitStream[j]==1) { return 0 }; break; //should be 0 spacer bit
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case 2: if (BitStream[j]==0) { return 0 }; break; //should be 1 spacer bit
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default: if (parityTest(parityWd, pLen, pType) == 0) { return 0; } break; //test parity
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}
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bitCnt+=(pLen-1);
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parityWd = 0;
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