mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 07:16:14 +08:00
tweaking felica timings to see if it gets better results
This commit is contained in:
parent
5025a18722
commit
4304372858
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@ -29,7 +29,8 @@
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// FeliCa timings
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// minimum time between the start bits of consecutive transfers from reader to tag: 6800 carrier (13.56MHz) cycles
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#ifndef FELICA_REQUEST_GUARD_TIME
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# define FELICA_REQUEST_GUARD_TIME (6800/16 + 1) // 426
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//# define FELICA_REQUEST_GUARD_TIME (6800 / 16 + 1) // 426
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# define FELICA_REQUEST_GUARD_TIME ((512 + 0 * 256) * 64 / 16 + 1)
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#endif
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// FRAME DELAY TIME 2672 carrier cycles
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#ifndef FELICA_FRAME_DELAY_TIME
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@ -64,6 +65,11 @@ static uint32_t iso18092_get_timeout(void) {
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#define FELICA_MAX_FRAME_SIZE 260
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#endif
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//structure to hold outgoing NFC frame
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static uint8_t frameSpace[FELICA_MAX_FRAME_SIZE + 4];
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@ -122,7 +128,9 @@ static void shiftInByte(uint8_t bt) {
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}
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static void Process18092Byte(uint8_t bt) {
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switch (FelicaFrame.state) {
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case STATE_UNSYNCD: {
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// almost any nonzero byte can be start of SYNC. SYNC should be preceded by zeros, but that is not always the case
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if (bt > 0) {
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@ -131,12 +139,15 @@ static void Process18092Byte(uint8_t bt) {
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}
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break;
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}
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case STATE_TRYING_SYNC: {
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if (bt == 0) {
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// desync
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FelicaFrame.shiftReg = bt;
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FelicaFrame.state = STATE_UNSYNCD;
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} else {
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for (uint8_t i = 0; i < 8; i++) {
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if (FelicaFrame.shiftReg == SYNC_16BIT) {
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@ -145,6 +156,7 @@ static void Process18092Byte(uint8_t bt) {
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FelicaFrame.framebytes[0] = 0xb2;
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FelicaFrame.framebytes[1] = 0x4d;
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FelicaFrame.byte_offset = i;
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// shift in remaining byte, slowly...
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for (uint8_t j = i; j < 8; j++) {
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FelicaFrame.framebytes[2] = (FelicaFrame.framebytes[2] << 1) + (bt & 1);
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@ -152,9 +164,10 @@ static void Process18092Byte(uint8_t bt) {
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}
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FelicaFrame.posCnt = 2;
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if (i == 0)
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if (i == 0) {
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break;
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}
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}
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FelicaFrame.shiftReg = (FelicaFrame.shiftReg << 1) + (bt & 1);
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bt >>= 1;
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}
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@ -351,16 +364,21 @@ static void BuildFliteRdblk(const uint8_t *idm, uint8_t blocknum, const uint16_t
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}
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static void TransmitFor18092_AsReader(const uint8_t *frame, uint16_t len, const uint32_t *NYI_timing_NYI, uint8_t power, uint8_t highspeed) {
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if (NYI_timing_NYI != NULL) {
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Dbprintf("Error: TransmitFor18092_AsReader does not check or set parameter NYI_timing_NYI");
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return;
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}
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uint16_t flags = FPGA_MAJOR_MODE_HF_ISO18092;
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if (power)
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if (power) {
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flags |= FPGA_HF_ISO18092_FLAG_READER;
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if (highspeed)
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}
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if (highspeed) {
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flags |= FPGA_HF_ISO18092_FLAG_424K;
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}
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FpgaWriteConfWord(flags);
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@ -419,9 +437,13 @@ static void TransmitFor18092_AsReader(const uint8_t *frame, uint16_t len, const
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// stop when button is pressed
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// or return TRUE when command is captured
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bool WaitForFelicaReply(uint16_t maxbytes) {
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if (g_dbglevel >= DBG_DEBUG)
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if (g_dbglevel >= DBG_DEBUG) {
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Dbprintf("WaitForFelicaReply Start");
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}
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uint32_t c = 0;
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// power, no modulation
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO18092 | FPGA_HF_ISO18092_FLAG_READER | FPGA_HF_ISO18092_FLAG_NOMOD);
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FelicaFrameReset();
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@ -433,12 +455,19 @@ bool WaitForFelicaReply(uint16_t maxbytes) {
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uint32_t timeout = iso18092_get_timeout();
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for (;;) {
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WDT_HIT();
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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b = (uint8_t)(AT91C_BASE_SSC->SSC_RHR);
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Process18092Byte(b);
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if (FelicaFrame.state == STATE_FULL) {
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felica_nexttransfertime = MAX(felica_nexttransfertime,
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felica_nexttransfertime = MAX(
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felica_nexttransfertime,
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(GetCountSspClk() & 0xfffffff8) - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER) / 16 + FELICA_FRAME_DELAY_TIME);
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LogTrace(
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@ -449,10 +478,15 @@ bool WaitForFelicaReply(uint16_t maxbytes) {
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NULL,
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false
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);
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if (g_dbglevel >= DBG_DEBUG) Dbprintf("All bytes received! STATE_FULL");
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return true;
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} else if (c++ > timeout && (FelicaFrame.state == STATE_UNSYNCD || FelicaFrame.state == STATE_TRYING_SYNC)) {
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if (g_dbglevel >= DBG_DEBUG) Dbprintf("Error: Timeout! STATE_UNSYNCD");
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return false;
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}
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}
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@ -478,8 +512,9 @@ static void iso18092_setup(uint8_t fpga_minor_mode) {
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// DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
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FelicaFrameinit(BigBuf_malloc(FELICA_MAX_FRAME_SIZE));
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felica_nexttransfertime = 2 * DELAY_ARM2AIR_AS_READER;
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iso18092_set_timeout(2120); // 106 * 20ms maximum start-up time of card
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felica_nexttransfertime = 2 * DELAY_ARM2AIR_AS_READER; // 418
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// iso18092_set_timeout(2120); // 106 * 20ms maximum start-up time of card
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iso18092_set_timeout(1060); // 106 * 10ms maximum start-up time of card
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init_table(CRC_FELICA);
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@ -118,7 +118,9 @@ static size_t lf_count_edge_periods_ex(size_t max, bool wait, bool detect_gap) {
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volatile uint8_t adc_val = AT91C_BASE_SSC->SSC_RHR;
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if (g_logging) logSampleSimple(adc_val);
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if (g_logging) {
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logSampleSimple(adc_val);
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}
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// Only test field changes if state of adc values matter
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if (wait == false) {
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@ -157,7 +159,10 @@ static size_t lf_count_edge_periods_ex(size_t max, bool wait, bool detect_gap) {
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}
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}
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if (g_logging) logSampleSimple(0xFF);
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if (g_logging) {
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logSampleSimple(0xFF);
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}
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return 0;
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}
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@ -210,16 +215,18 @@ void lf_init(bool reader, bool simulate, bool ledcontrol) {
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sc->averaging = 0;
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
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if (reader) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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} else {
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if (simulate)
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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else
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// Sniff
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//FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE);
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if (simulate) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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} else {
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// Sniff
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC);
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// FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE);
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}
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}
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// Connect the A/D to the peak-detected low-frequency path.
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@ -261,7 +268,9 @@ void lf_init(bool reader, bool simulate, bool ledcontrol) {
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uint32_t bufsize = 10000;
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// use malloc
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if (g_logging) initSampleBufferEx(&bufsize, true);
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if (g_logging) {
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initSampleBufferEx(&bufsize, true);
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}
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lf_sample_mean();
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}
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@ -246,12 +246,13 @@ void logSample(uint8_t sample, uint8_t decimation, uint8_t bits_per_sample, bool
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**/
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void LFSetupFPGAForADC(int divisor, bool reader_field) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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if ((divisor == 1) || (divisor < 0) || (divisor > 255))
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if ((divisor == 1) || (divisor < 0) || (divisor > 255)) {
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
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else if (divisor == 0)
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} else if (divisor == 0) {
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
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else
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} else {
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
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}
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | (reader_field ? FPGA_LF_ADC_READER_FIELD : 0));
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// skip until first high samples begin to change
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if (startFound || sample > T55xx_READ_LOWER_THRESHOLD + T55xx_READ_TOL) {
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// if just found start - recover last sample
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if (!startFound) {
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if (startFound == false) {
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dest[i++] = lastSample;
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startFound = true;
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}
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// collect samples
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if (i < bufsize) {
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dest[i++] = sample;
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}
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}
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}
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}
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}
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/**
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* acquisition of Cotag LF signal. Similart to other LF, since the Cotag has such long datarate RF/384
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* and is Manchester?, we directly gather the manchester data into bigbuff
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firstlow = true;
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}
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++i;
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if (sample > COTAG_ONE_THRESHOLD) {
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dest[i] = 255;
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++i;
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} else if (sample < COTAG_ZERO_THRESHOLD) {
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dest[i] = 0;
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++i;
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} else {
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dest[i] = dest[i - 1];
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++i;
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}
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}
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}
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}
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//convert hex digit to integer
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uint8_t hex2int(char hexchar) {
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switch (hexchar) {
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uint8_t hex2int(char x) {
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switch (x) {
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case '0':
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return 0;
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break;
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case '1':
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return 1;
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break;
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case '2':
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return 2;
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break;
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case '3':
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return 3;
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break;
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case '4':
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return 4;
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break;
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case '5':
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return 5;
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break;
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case '6':
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return 6;
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break;
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case '7':
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return 7;
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break;
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case '8':
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return 8;
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break;
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case '9':
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return 9;
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break;
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case 'a':
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case 'A':
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return 10;
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break;
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case 'b':
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case 'B':
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return 11;
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break;
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case 'c':
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case 'C':
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return 12;
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break;
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case 'd':
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case 'D':
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return 13;
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break;
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case 'e':
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case 'E':
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return 14;
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break;
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case 'f':
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case 'F':
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return 15;
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break;
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default:
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return 0;
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}
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}
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/*
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The following methods comes from Rfidler sourcecode.
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https://github.com/ApertureLabsLtd/RFIDler/blob/master/firmware/Pic32/RFIDler.X/src/
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*/
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// convert hex to sequence of 0/1 bit values
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// returns number of bits converted
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int hex2binarray(char *target, char *source) {
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return hex2binarray_n(target, source, strlen(source));
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}
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int hex2binarray_n(char *target, char *source, int sourcelen) {
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int count = 0;
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// process 4 bits (1 hex digit) at a time
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while (sourcelen--) {
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char x = *(source++);
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*(target++) = (x >> 7) & 1;
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*(target++) = (x >> 6) & 1;
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*(target++) = (x >> 5) & 1;
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*(target++) = (x >> 4) & 1;
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*(target++) = (x >> 3) & 1;
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*(target++) = (x >> 2) & 1;
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*(target++) = (x >> 1) & 1;
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*(target++) = (x & 1);
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count += 8;
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}
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return count;
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}
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int binarray2hex(const uint8_t *bs, int bs_len, uint8_t *hex) {
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int count = 0;
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int byte_index = 0;
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// Clear output buffer
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memset(hex, 0, bs_len >> 3);
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for (int i = 0; i < bs_len; i++) {
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// Set the appropriate bit in hex
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if (bs[i] == 1) {
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hex[byte_index] |= (1 << (7 - (count % 8)));
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}
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count++;
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// Move to the next byte if 8 bits have been filled
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if (count % 8 == 0) {
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byte_index++;
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}
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}
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return count;
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}
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void LEDsoff(void) {
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LED_A_OFF();
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LED_B_OFF();
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@ -82,9 +82,12 @@
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#endif
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size_t nbytes(size_t nbits);
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uint8_t hex2int(char hexchar);
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int hex2binarray(char *target, char *source);
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int hex2binarray_n(char *target, char *source, int sourcelen);
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int binarray2hex(const uint8_t *bs, int bs_len, uint8_t *hex);
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void LED(int led, int ms);
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void LEDsoff(void);
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void SpinOff(uint32_t pause);
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