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same param names
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commit
48f7b3bdb6
1 changed files with 7 additions and 4 deletions
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@ -200,7 +200,7 @@ void logSample(uint8_t sample, uint8_t decimation, uint8_t bits_per_sample, bool
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* 0 or 95 ==> 125 kHz
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*
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**/
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void LFSetupFPGAForADC(int divisor, bool lf_field) {
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void LFSetupFPGAForADC(int divisor, bool reader_field) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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if ((divisor == 1) || (divisor < 0) || (divisor > 255))
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
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@ -209,14 +209,17 @@ void LFSetupFPGAForADC(int divisor, bool lf_field) {
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else
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | (reader_field ? FPGA_LF_ADC_READER_FIELD : 0));
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// 50ms for the resonant antenna to settle.
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if (reader_field)
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SpinDelay(50);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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// start a 1.5ticks is 1us
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StartTicks();
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}
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@ -333,11 +336,11 @@ uint32_t DoPartialAcquisition(int trigger_threshold, bool verbose, uint32_t samp
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return DoAcquisition(1, 8, 0, trigger_threshold, verbose, sample_size, cancel_after, 0);
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}
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uint32_t ReadLF(bool activeField, bool verbose, uint32_t sample_size) {
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uint32_t ReadLF(bool reader_field, bool verbose, uint32_t sample_size) {
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if (verbose)
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printConfig();
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LFSetupFPGAForADC(config.divisor, activeField);
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LFSetupFPGAForADC(config.divisor, reader_field);
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uint32_t ret = DoAcquisition_config(verbose, sample_size);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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return ret;
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