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More compact notation

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Alex 2023-08-29 11:24:56 +02:00
parent 44fc77ec3b
commit 61765cc933
1 changed files with 1 additions and 4 deletions
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5
fpga/lo_read.v
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@ -54,10 +54,7 @@ begin
if ((pck_cnt == 8'd7) && !pck_divclk)
to_arm_shiftreg <= adc_d;
else
begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
to_arm_shiftreg[0] <= 1'b0;
end
to_arm_shiftreg <= {to_arm_shiftreg[6:0], 1'b0};
end
// ADC samples on falling edge of adc_clk, data available on the rising edge