RfidResearchGroup/proxmark3
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FIX: the underlaying bug on deviceside code. The SSPCLOCK wasn't reset to zero sometimes. More specific, TC2 wasn't reset cause all sorts of timing issues for the device side randomly. Like 'hf mf mifare', like iclass, like 'hf mf sim' etc etc.

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This commit is contained in:
iceman1001 2016-08-24 12:37:31 +02:00
parent a1ab594e24
commit 63a1d80130
1 changed files with 10 additions and 4 deletions
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14
armsrc/util.c
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@ -400,9 +400,9 @@ void StartCountSspClk() {
| AT91C_TC_WAVE // Waveform Mode
| AT91C_TC_WAVESEL_UP; // just count
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC0
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC1
AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC2
// synchronize the counter with the ssp_frame signal.
// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
@ -420,7 +420,13 @@ void StartCountSspClk() {
// The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
// Therefore need to wait quite some time before we can use the counter.
while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
while (AT91C_BASE_TC2->TC_CV >= 1);
}
void ResetSspClk(void) {
//enable clock of timer and software trigger
AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
AT91C_BASE_TC2->TC_CCR = AT91C_TC_SWTRG;
}
uint32_t RAMFUNC GetCountSspClk(){