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https://github.com/RfidResearchGroup/proxmark3.git
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CHG: name changes
This commit is contained in:
iceman1001
parent
2612cd006a
commit
6743e45386
1 changed files with 23 additions and 25 deletions
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@ -29,27 +29,25 @@ static uint32_t felica_timeout;
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static uint32_t felica_nexttransfertime;
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static uint32_t felica_lasttime_prox2air_start;
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static void felica_setup(uint8_t fpga_minor_mode);
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static void iso18092_setup(uint8_t fpga_minor_mode);
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static uint8_t felica_select_card(felica_card_select_t *card);
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static void TransmitFor18092_AsReader(uint8_t * frame, int len, uint32_t *timing, uint8_t power, uint8_t highspeed);
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bool WaitForFelicaReply(uint16_t maxbytes);
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void felica_set_timeout(uint32_t timeout) {
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void iso18092_set_timeout(uint32_t timeout) {
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felica_timeout = timeout + (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) + 2;
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}
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uint32_t felica_get_timeout(void) {
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uint32_t iso18092_get_timeout(void) {
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return felica_timeout - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) - 2;
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}
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//random service RW: 0x0009
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//random service RO: 0x000B
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#ifndef NFC_MAX_FRAME_SIZE
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#define NFC_MAX_FRAME_SIZE 260
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#ifndef FELICA_MAX_FRAME_SIZE
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#define FELICA_MAX_FRAME_SIZE 260
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#endif
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//structure to hold outgoing NFC frame
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static uint8_t frameSpace[NFC_MAX_FRAME_SIZE+4];
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static uint8_t frameSpace[FELICA_MAX_FRAME_SIZE+4];
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//structure to hold incoming NFC frame, used for ISO/IEC 18092-compatible frames
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static struct {
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@ -85,7 +83,7 @@ static void FelicaFrameReset() {
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FelicaFrame.crc_ok = false;
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FelicaFrame.byte_offset = 0;
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}
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static void NFCInit(uint8_t *data) {
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static void FelicaFrameinit(uint8_t *data) {
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FelicaFrame.framebytes = data;
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FelicaFrameReset();
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}
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@ -105,7 +103,7 @@ static void shiftInByte(uint8_t bt) {
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}
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}
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static void ProcessNFCByte(uint8_t bt) {
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static void Process18092Byte(uint8_t bt) {
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switch (FelicaFrame.state) {
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case STATE_UNSYNCD: {
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//almost any nonzero byte can be start of SYNC. SYNC should be preceded by zeros, but that is not alsways the case
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@ -127,7 +125,7 @@ static void ProcessNFCByte(uint8_t bt) {
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//SYNC done!
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FelicaFrame.state = STATE_GET_LENGTH;
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FelicaFrame.framebytes[0] = 0xb2;
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FelicaFrame.framebytes[1] = 0x4d; //write SYNC
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FelicaFrame.framebytes[1] = 0x4d;
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FelicaFrame.byte_offset = i;
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//shift in remaining byte, slowly...
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for(uint8_t j=i; j<8; j++) {
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@ -269,7 +267,7 @@ static uint8_t felica_select_card(felica_card_select_t *card) {
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static void BuildFliteRdblk(uint8_t* idm, int blocknum, uint16_t *blocks ) {
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if (blocknum > 4 || blocknum <= 0)
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Dbprintf("Invalid number of blocks, %d. Up to 4 are allowed.", blocknum);
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Dbprintf("Invalid number of blocks, %d != 4", blocknum);
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uint8_t c = 0, i = 0;
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@ -394,13 +392,13 @@ bool WaitForFelicaReply(uint16_t maxbytes) {
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// clear RXRDY:
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uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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uint32_t timeout = felica_get_timeout();
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uint32_t timeout = iso18092_get_timeout();
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for(;;) {
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WDT_HIT();
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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b = (uint8_t)(AT91C_BASE_SSC->SSC_RHR);
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ProcessNFCByte(b);
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Process18092Byte(b);
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if (FelicaFrame.state == STATE_FULL) {
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felica_nexttransfertime =
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MAX(
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@ -432,7 +430,7 @@ bool WaitForFelicaReply(uint16_t maxbytes) {
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// Set up FeliCa communication (similar to iso14443a_setup)
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// field is setup for "Sending as Reader"
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static void felica_setup(uint8_t fpga_minor_mode) {
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static void iso18092_setup(uint8_t fpga_minor_mode) {
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LEDsoff();
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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@ -442,11 +440,13 @@ static void felica_setup(uint8_t fpga_minor_mode) {
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// Initialize Demod and Uart structs
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//DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
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NFCInit(BigBuf_malloc(NFC_MAX_FRAME_SIZE));
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FelicaFrameinit(BigBuf_malloc(FELICA_MAX_FRAME_SIZE));
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felica_nexttransfertime = 2 * DELAY_ARM2AIR_AS_READER;
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felica_set_timeout(2120); // 106 * 20ms maximum start-up time of card
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iso18092_set_timeout(2120); // 106 * 20ms maximum start-up time of card
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init_table(CRC_FELICA);
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// connect Demodulated Signal to ADC:
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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@ -455,8 +455,6 @@ static void felica_setup(uint8_t fpga_minor_mode) {
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// LSB transfer. Remember to set it back to MSB with
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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init_table(CRC_FELICA);
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// Signal field is on with the appropriate LED
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FpgaWriteConfWord(FPGA_MAJOR_MODE_ISO18092 | fpga_minor_mode);
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@ -492,7 +490,7 @@ void felica_sendraw(UsbCommand *c) {
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set_tracing(true);
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if ((param & FELICA_CONNECT)) {
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felica_setup(FPGA_HF_ISO18092_FLAG_READER | FPGA_HF_ISO18092_FLAG_NOMOD);
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iso18092_setup(FPGA_HF_ISO18092_FLAG_READER | FPGA_HF_ISO18092_FLAG_NOMOD);
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// notify client selecting status.
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// if failed selecting, turn off antenna and quite.
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@ -547,7 +545,7 @@ void felica_sniff(uint32_t samplesToSkip, uint32_t triggersToSkip) {
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Dbprintf("Snoop FelicaLiteS: Getting first %d frames, Skipping %d triggers.\n", samplesToSkip, triggersToSkip);
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felica_setup( FPGA_HF_ISO18092_FLAG_NOMOD);
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iso18092_setup( FPGA_HF_ISO18092_FLAG_NOMOD);
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//the frame bits are slow enough.
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int n = BigBuf_max_traceLen() / sizeof(uint8_t); // take all memory
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@ -563,7 +561,7 @@ void felica_sniff(uint32_t samplesToSkip, uint32_t triggersToSkip) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
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uint8_t dist = (uint8_t)(AT91C_BASE_SSC->SSC_RHR);
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ProcessNFCByte(dist);
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Process18092Byte(dist);
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//to be sure we are in frame
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if (FelicaFrame.state == STATE_GET_LENGTH) {
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@ -643,7 +641,7 @@ void felica_sim_lite(uint64_t nfcid) {
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AddCrc(resp_poll1, resp_poll1[2]);
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AddCrc(resp_readblk, resp_readblk[2]);
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felica_setup( FPGA_HF_ISO18092_FLAG_NOMOD);
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iso18092_setup( FPGA_HF_ISO18092_FLAG_NOMOD);
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bool listenmode = true;
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//uint32_t frtm = GetCountSspClk();
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@ -657,7 +655,7 @@ void felica_sim_lite(uint64_t nfcid) {
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uint8_t dist = (uint8_t)(AT91C_BASE_SSC->SSC_RHR);
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//frtm = GetCountSspClk();
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ProcessNFCByte(dist);
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Process18092Byte(dist);
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if (FelicaFrame.state == STATE_FULL) {
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@ -725,7 +723,7 @@ void felica_dump_lite_s() {
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uint16_t liteblks[28] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x90,0x91,0x92,0xa0};
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// setup device.
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felica_setup(FPGA_HF_ISO18092_FLAG_READER | FPGA_HF_ISO18092_FLAG_NOMOD);
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iso18092_setup(FPGA_HF_ISO18092_FLAG_READER | FPGA_HF_ISO18092_FLAG_NOMOD);
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uint8_t blknum;
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bool isOK = false;
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