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FPGA Hi-Simulate: Formatted code
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@ -59,7 +59,7 @@ always @(posedge adc_clk)
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ssp_clk_divider <= (ssp_clk_divider + 1);
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ssp_clk_divider <= (ssp_clk_divider + 1);
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reg ssp_clk;
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reg ssp_clk;
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reg ssp_frame;
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always @(negedge adc_clk)
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always @(negedge adc_clk)
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begin
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begin
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//If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
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//If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
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@ -81,8 +81,6 @@ begin
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end
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end
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//assign ssp_clk = ssp_clk_divider[4];
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// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
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// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
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// this is arbitrary, because it's just a bitstream.
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// this is arbitrary, because it's just a bitstream.
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// One nasty issue, though: I can't make it work with both rx and tx at
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// One nasty issue, though: I can't make it work with both rx and tx at
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@ -96,7 +94,7 @@ always @(negedge ssp_clk)
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ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
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ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
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reg ssp_frame;
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always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
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always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
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if(mod_type == 3'b000) // not modulating, so listening, to ARM
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if(mod_type == 3'b000) // not modulating, so listening, to ARM
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ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
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ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
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@ -134,8 +132,5 @@ assign pwr_oe4 = modulating_carrier;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign dbg = modulating_carrier;
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assign dbg = modulating_carrier;
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//reg dbg;
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//always @(ssp_dout)
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// dbg <= ssp_dout;
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endmodule
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endmodule
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