From 72dd4d5ddeb19f19bb40de8459894f18d5f985bf Mon Sep 17 00:00:00 2001
From: iceman1001 <iceman@iuse.se>
Date: Thu, 18 Apr 2019 09:27:38 +0200
Subject: [PATCH] chg: 'fpga lf sim' - 25% both on sides.

---
 fpga/lo_simulate.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/lo_simulate.v b/fpga/lo_simulate.v
index 57e602a2b..687bed27c 100644
--- a/fpga/lo_simulate.v
+++ b/fpga/lo_simulate.v
@@ -64,7 +64,7 @@ reg output_state;
 always @(posedge pck0)
 begin
 	if((pck_divider == 8'd7) && !clk_state) begin
-		is_high = (adc_d >= 8'd200);
+		is_high = (adc_d >= 8'd191);
 		is_low = (adc_d <= 8'd64);
 	end
 end