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pwr_oe2 is LF

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iceman1001 2020-10-02 19:42:19 +02:00
parent 2b4124d665
commit 7eadc900c1
1 changed files with 4 additions and 3 deletions
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7
fpga/hi_flite.v
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@ -39,6 +39,7 @@ wire disabl = mod_type[0];
// Most off, oe4 for modulation; // Most off, oe4 for modulation;
// Trying reader emulation (would presumably just require switching power on, but I am not sure) // Trying reader emulation (would presumably just require switching power on, but I am not sure)
assign pwr_lo = 1'b0; assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
// 512x64/fc -wait before ts0, 32768 ticks // 512x64/fc -wait before ts0, 32768 ticks
// tslot: 256*64/fc // tslot: 256*64/fc
@ -339,7 +340,6 @@ end
//put modulation here to maintain the correct clock. Seems that some readers are sensitive to that //put modulation here to maintain the correct clock. Seems that some readers are sensitive to that
reg pwr_hi; reg pwr_hi;
reg pwr_oe1; reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3; reg pwr_oe3;
reg pwr_oe4; reg pwr_oe4;
@ -351,7 +351,6 @@ begin
begin begin
pwr_hi <= ck_1356meg; pwr_hi <= ck_1356meg;
pwr_oe1 <= 1'b0;//mod; pwr_oe1 <= 1'b0;//mod;
pwr_oe2 <= 1'b0;//mod;
pwr_oe3 <= 1'b0;//mod; pwr_oe3 <= 1'b0;//mod;
pwr_oe4 <= mod;//1'b0; pwr_oe4 <= mod;//1'b0;
end end
@ -359,10 +358,12 @@ begin
begin begin
pwr_hi <= 1'b0; pwr_hi <= 1'b0;
pwr_oe1 <= 1'b0; pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0; pwr_oe3 <= 1'b0;
pwr_oe4 <= mod; pwr_oe4 <= mod;
end end
end end
endmodule endmodule