diff --git a/fpga/fpga.bit b/fpga/fpga.bit
index d3a418089..503f041fb 100644
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ
diff --git a/fpga/fpga.v b/fpga/fpga.v
index 8f8f38250..b22c9d5c7 100644
--- a/fpga/fpga.v
+++ b/fpga/fpga.v
@@ -138,7 +138,7 @@ lo_simulate ls(
 	adc_d, ls_adc_clk,
 	ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
 	cross_hi, cross_lo,
-	ls_dbg
+	ls_dbg, divisor
 );
 
 hi_read_tx ht(
diff --git a/fpga/lo_simulate.v b/fpga/lo_simulate.v
index 7eb910ba1..9e3cd50ab 100644
--- a/fpga/lo_simulate.v
+++ b/fpga/lo_simulate.v
@@ -12,7 +12,8 @@ module lo_simulate(
     adc_d, adc_clk,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
-    dbg
+    dbg,
+	 divisor
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -21,7 +22,8 @@ module lo_simulate(
     input ssp_dout;
     output ssp_frame, ssp_din, ssp_clk;
     input cross_hi, cross_lo;
-    output dbg;
+    output dbg;
+	 input [7:0] divisor;
 
 // No logic, straight through.
 assign pwr_oe3 = 1'b0;
@@ -30,8 +32,51 @@ assign pwr_oe2 = ssp_dout;
 assign pwr_oe4 = ssp_dout;
 assign ssp_clk = cross_lo;
 assign pwr_lo = 1'b0;
-assign adc_clk = 1'b0;
 assign pwr_hi = 1'b0;
-assign dbg = cross_lo;
+assign dbg = ssp_frame;
+
+// Divide the clock to be used for the ADC
+reg [7:0] pck_divider;
+reg clk_state;
+
+always @(posedge pck0)
+begin
+	if(pck_divider == divisor[7:0])
+		begin
+			pck_divider <= 8'd0;
+			clk_state = !clk_state;
+		end
+	else
+	begin
+		pck_divider <= pck_divider + 1;
+	end
+end
+
+assign adc_clk = ~clk_state;
+
+// Toggle the output with hysteresis
+//  Set to high if the ADC value is above 200
+//  Set to low if the ADC value is below 64
+reg is_high;
+reg is_low;
+reg output_state;
+
+always @(posedge pck0)
+begin
+	if((pck_divider == 8'd7) && !clk_state) begin
+		is_high = (adc_d >= 8'd200);
+		is_low = (adc_d <= 8'd64);
+	end
+end
+
+always @(posedge is_high or posedge is_low)
+begin
+	if(is_high)
+		output_state <= 1'd1;
+	else if(is_low)
+		output_state <= 1'd0;
+end
+
+assign ssp_frame = output_state;
 
 endmodule