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Merge pull request #87 from timhir/master

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Improved logic for determining the correct Frame Delay Time (FDT)
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Iceman 2017-03-06 11:15:25 +01:00 committed by GitHub
commit 81f9cbb188
1 changed files with 10 additions and 3 deletions
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13
armsrc/iso14443a.c
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@ -1604,9 +1604,16 @@ int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
// Modulate Manchester // Modulate Manchester
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
// include correction bit if necessary // Include correction bit if necessary
if (Uart.parityBits & 0x01) { if (Uart.bitCount == 7)
correctionNeeded = TRUE; {
// Short tags (7 bits) don't have parity, determine the correct value from MSB
correctionNeeded = Uart.output[0] & 0x40;
}
else
{
// The parity bits are left-aligned
correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
} }
// 1236, so correction bit needed // 1236, so correction bit needed
i = (correctionNeeded) ? 0 : 1; i = (correctionNeeded) ? 0 : 1;