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#defines for ADC channels so we can see what's what

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adam@algroup.co.uk 2009-07-06 16:40:03 +00:00
parent 1de3416e5a
commit 846225d575
2 changed files with 6 additions and 4 deletions
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8
armsrc/appmain.c
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@ -249,7 +249,7 @@ void SweepLFrange()
for (i=255; i>19; i--) { for (i=255; i>19; i--) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);
SpinDelay(20); SpinDelay(20);
dest[i] = (137500 * AvgAdc(4)) >> 18; dest[i] = (137500 * AvgAdc(ADC_CHAN_LF)) >> 18;
} }
} }
@ -267,7 +267,7 @@ void MeasureAntennaTuning(void)
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
SpinDelay(20); SpinDelay(20);
vLf125 = AvgAdc(4); vLf125 = AvgAdc(ADC_CHAN_LF);
// Vref = 3.3V, and a 10000:240 voltage divider on the input // Vref = 3.3V, and a 10000:240 voltage divider on the input
// can measure voltages up to 137500 mV // can measure voltages up to 137500 mV
vLf125 = (137500 * vLf125) >> 10; vLf125 = (137500 * vLf125) >> 10;
@ -276,7 +276,7 @@ void MeasureAntennaTuning(void)
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
SpinDelay(20); SpinDelay(20);
vLf134 = AvgAdc(4); vLf134 = AvgAdc(ADC_CHAN_LF);
// Vref = 3.3V, and a 10000:240 voltage divider on the input // Vref = 3.3V, and a 10000:240 voltage divider on the input
// can measure voltages up to 137500 mV // can measure voltages up to 137500 mV
vLf134 = (137500 * vLf134) >> 10; vLf134 = (137500 * vLf134) >> 10;
@ -284,7 +284,7 @@ void MeasureAntennaTuning(void)
// Let the FPGA drive the high-frequency antenna around 13.56 MHz. // Let the FPGA drive the high-frequency antenna around 13.56 MHz.
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
SpinDelay(20); SpinDelay(20);
vHf = AvgAdc(5); vHf = AvgAdc(ADC_CHAN_HF);
// Vref = 3300mV, and an 10:1 voltage divider on the input // Vref = 3300mV, and an 10:1 voltage divider on the input
// can measure voltages up to 33000 mV // can measure voltages up to 33000 mV
vHf = (33000 * vHf) >> 10; vHf = (33000 * vHf) >> 10;

2
include/at91sam7s128.h
View file

@ -381,6 +381,8 @@
#define ADC_END_OF_RX_BUFFER (1<<18) #define ADC_END_OF_RX_BUFFER (1<<18)
#define ADC_RX_BUFFER_FULL (1<<19) #define ADC_RX_BUFFER_FULL (1<<19)
#define ADC_CHAN_LF 4
#define ADC_CHAN_HF 5
//------------- //-------------
// Synchronous Serial Controller // Synchronous Serial Controller