From 8a53137ab0bf0070776db843eaf81cec6ac2f3f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Dr=C3=B6scher?= Date: Sun, 29 Jul 2018 11:57:24 +0200 Subject: [PATCH] change: remove dead legic code This code was either disabled or never reached. --- armsrc/legicrf.c | 762 +---------------------------------------------- 1 file changed, 1 insertion(+), 761 deletions(-) diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c index dc4c8d4f6..035e01e98 100644 --- a/armsrc/legicrf.c +++ b/armsrc/legicrf.c @@ -30,43 +30,8 @@ static int legic_phase_drift; static int legic_frame_drift; static int legic_reqresp_drift; -AT91PS_TC timer; -AT91PS_TC prng_timer; -/* -static void setup_timer(void) { - // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging - // this it won't be terribly accurate but should be good enough. - // - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); - timer = AT91C_BASE_TC1; - timer->TC_CCR = AT91C_TC_CLKDIS; - timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; - timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; - // - // Set up Timer 2 to use for measuring time between frames in - // tag simulation mode. Runs 4x faster as Timer 1 - // - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2); - prng_timer = AT91C_BASE_TC2; - prng_timer->TC_CCR = AT91C_TC_CLKDIS; - prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK; - prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; -} - - AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14); - AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; - - // fast clock - AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable - AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks - AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | - AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; - AT91C_BASE_TC0->TC_RA = 1; - AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 - -*/ // At TIMER_CLOCK3 (MCK/32) // testing calculating in ticks. 1.5ticks = 1us @@ -126,20 +91,9 @@ static void frame_clean(struct legic_frame * const f) { f->bits = 0; } -// Prng works when waiting in 99.1us cycles. -// and while sending/receiving in bit frames (100, 60) -/*static void CalibratePrng( uint32_t time){ - // Calculate Cycles based on timer 100us - uint32_t i = (time - sendFrameStop) / 100 ; - // substract cycles of finished frames - int k = i - legic_prng_count()+1; - // substract current frame length, rewind to beginning - if ( k > 0 ) - legic_prng_forward(k); } -*/ /* Generate Keystream */ uint32_t get_key_stream(int skip, int count) { @@ -575,36 +529,7 @@ int legic_select_card(legic_card_select_t *p_card){ } //----------------------------------------------------------------------------- -// Work with emulator memory -// -// Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not -// involved in dealing with emulator memory. But if it is called later, it might -// destroy the Emulator Memory. //----------------------------------------------------------------------------- -// arg0 = offset -// arg1 = num of bytes -void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) { - FpgaDownloadAndGo(FPGA_BITSTREAM_HF); - legic_emlset_mem(data, arg0, arg1); -} -// arg0 = offset -// arg1 = num of bytes -void LegicEMemGet(uint32_t arg0, uint32_t arg1) { - FpgaDownloadAndGo(FPGA_BITSTREAM_HF); - uint8_t buf[USB_CMD_DATA_SIZE] = {0x00}; - legic_emlget_mem(buf, arg0, arg1); - LED_B_ON(); - cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE); - LED_B_OFF(); -} -void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) { - cardmem = BigBuf_get_EM_addr(); - memcpy(cardmem + offset, data, numofbytes); -} -void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) { - cardmem = BigBuf_get_EM_addr(); - memcpy(data, cardmem + offset, numofbytes); -} void LegicRfInfo(void){ @@ -932,691 +857,6 @@ void LegicRfSimulate(int phase, int frame, int reqresp) LEDsoff(); cmd_send(CMD_ACK, 1, 0, 0, 0, 0); } - - -//----------------------------------------------------------------------------- -// Code up a string of octets at layer 2 (including CRC, we don't generate -// that here) so that they can be transmitted to the reader. Doesn't transmit -// them yet, just leaves them ready to send in ToSend[]. -//----------------------------------------------------------------------------- -// static void CodeLegicAsTag(const uint8_t *cmd, int len) -// { - // int i; - - // ToSendReset(); - - // // Transmit a burst of ones, as the initial thing that lets the - // // reader get phase sync. This (TR1) must be > 80/fs, per spec, - // // but tag that I've tried (a Paypass) exceeds that by a fair bit, - // // so I will too. - // for(i = 0; i < 20; i++) { - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // } - - // // Send SOF. - // for(i = 0; i < 10; i++) { - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // } - // for(i = 0; i < 2; i++) { - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // } - - // for(i = 0; i < len; i++) { - // int j; - // uint8_t b = cmd[i]; - - // // Start bit - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - - // // Data bits - // for(j = 0; j < 8; j++) { - // if(b & 1) { - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // } else { - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // } - // b >>= 1; - // } - - // // Stop bit - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // } - - // // Send EOF. - // for(i = 0; i < 10; i++) { - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // ToSendStuffBit(0); - // } - // for(i = 0; i < 2; i++) { - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // ToSendStuffBit(1); - // } - - // // Convert from last byte pos to length - // ToSendMax++; -// } - -//----------------------------------------------------------------------------- -// The software UART that receives commands from the reader, and its state -// variables. -//----------------------------------------------------------------------------- -/* -static struct { - enum { - STATE_UNSYNCD, - STATE_GOT_FALLING_EDGE_OF_SOF, - STATE_AWAITING_START_BIT, - STATE_RECEIVING_DATA - } state; - uint16_t shiftReg; - int bitCnt; - int byteCnt; - int byteCntMax; - int posCnt; - uint8_t *output; -} Uart; -*/ -/* Receive & handle a bit coming from the reader. - * - * This function is called 4 times per bit (every 2 subcarrier cycles). - * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us - * - * LED handling: - * LED A -> ON once we have received the SOF and are expecting the rest. - * LED A -> OFF once we have received EOF or are in error state or unsynced - * - * Returns: true if we received a EOF - * false if we are still waiting for some more - */ -// static RAMFUNC int HandleLegicUartBit(uint8_t bit) -// { - // switch(Uart.state) { - // case STATE_UNSYNCD: - // if(!bit) { - // // we went low, so this could be the beginning of an SOF - // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF; - // Uart.posCnt = 0; - // Uart.bitCnt = 0; - // } - // break; - - // case STATE_GOT_FALLING_EDGE_OF_SOF: - // Uart.posCnt++; - // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit - // if(bit) { - // if(Uart.bitCnt > 9) { - // // we've seen enough consecutive - // // zeros that it's a valid SOF - // Uart.posCnt = 0; - // Uart.byteCnt = 0; - // Uart.state = STATE_AWAITING_START_BIT; - // LED_A_ON(); // Indicate we got a valid SOF - // } else { - // // didn't stay down long enough - // // before going high, error - // Uart.state = STATE_UNSYNCD; - // } - // } else { - // // do nothing, keep waiting - // } - // Uart.bitCnt++; - // } - // if(Uart.posCnt >= 4) Uart.posCnt = 0; - // if(Uart.bitCnt > 12) { - // // Give up if we see too many zeros without - // // a one, too. - // LED_A_OFF(); - // Uart.state = STATE_UNSYNCD; - // } - // break; - - // case STATE_AWAITING_START_BIT: - // Uart.posCnt++; - // if(bit) { - // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs - // // stayed high for too long between - // // characters, error - // Uart.state = STATE_UNSYNCD; - // } - // } else { - // // falling edge, this starts the data byte - // Uart.posCnt = 0; - // Uart.bitCnt = 0; - // Uart.shiftReg = 0; - // Uart.state = STATE_RECEIVING_DATA; - // } - // break; - - // case STATE_RECEIVING_DATA: - // Uart.posCnt++; - // if(Uart.posCnt == 2) { - // // time to sample a bit - // Uart.shiftReg >>= 1; - // if(bit) { - // Uart.shiftReg |= 0x200; - // } - // Uart.bitCnt++; - // } - // if(Uart.posCnt >= 4) { - // Uart.posCnt = 0; - // } - // if(Uart.bitCnt == 10) { - // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001)) - // { - // // this is a data byte, with correct - // // start and stop bits - // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff; - // Uart.byteCnt++; - - // if(Uart.byteCnt >= Uart.byteCntMax) { - // // Buffer overflowed, give up - // LED_A_OFF(); - // Uart.state = STATE_UNSYNCD; - // } else { - // // so get the next byte now - // Uart.posCnt = 0; - // Uart.state = STATE_AWAITING_START_BIT; - // } - // } else if (Uart.shiftReg == 0x000) { - // // this is an EOF byte - // LED_A_OFF(); // Finished receiving - // Uart.state = STATE_UNSYNCD; - // if (Uart.byteCnt != 0) { - // return TRUE; - // } - // } else { - // // this is an error - // LED_A_OFF(); - // Uart.state = STATE_UNSYNCD; - // } - // } - // break; - - // default: - // LED_A_OFF(); - // Uart.state = STATE_UNSYNCD; - // break; - // } - - // return false; -// } -/* - -static void UartReset() { - Uart.byteCntMax = 3; - Uart.state = STATE_UNSYNCD; - Uart.byteCnt = 0; - Uart.bitCnt = 0; - Uart.posCnt = 0; - memset(Uart.output, 0x00, 3); -} -*/ -// static void UartInit(uint8_t *data) { - // Uart.output = data; - // UartReset(); -// } - -//============================================================================= -// An LEGIC reader. We take layer two commands, code them -// appropriately, and then send them to the tag. We then listen for the -// tag's response, which we leave in the buffer to be demodulated on the -// PC side. -//============================================================================= -/* -static struct { - enum { - DEMOD_UNSYNCD, - DEMOD_PHASE_REF_TRAINING, - DEMOD_AWAITING_FALLING_EDGE_OF_SOF, - DEMOD_GOT_FALLING_EDGE_OF_SOF, - DEMOD_AWAITING_START_BIT, - DEMOD_RECEIVING_DATA - } state; - int bitCount; - int posCount; - int thisBit; - uint16_t shiftReg; - uint8_t *output; - int len; - int sumI; - int sumQ; -} Demod; -*/ -/* - * Handles reception of a bit from the tag - * - * This function is called 2 times per bit (every 4 subcarrier cycles). - * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us - * - * LED handling: - * LED C -> ON once we have received the SOF and are expecting the rest. - * LED C -> OFF once we have received EOF or are unsynced - * - * Returns: true if we received a EOF - * false if we are still waiting for some more - * - */ - -/* -static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq) -{ - int v = 0; - int ai = ABS(ci); - int aq = ABS(cq); - int halfci = (ai >> 1); - int halfcq = (aq >> 1); - - switch(Demod.state) { - case DEMOD_UNSYNCD: - - CHECK_FOR_SUBCARRIER() - - if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected - Demod.state = DEMOD_PHASE_REF_TRAINING; - Demod.sumI = ci; - Demod.sumQ = cq; - Demod.posCount = 1; - } - break; - - case DEMOD_PHASE_REF_TRAINING: - if(Demod.posCount < 8) { - - CHECK_FOR_SUBCARRIER() - - if (v > SUBCARRIER_DETECT_THRESHOLD) { - // set the reference phase (will code a logic '1') by averaging over 32 1/fs. - // note: synchronization time > 80 1/fs - Demod.sumI += ci; - Demod.sumQ += cq; - ++Demod.posCount; - } else { - // subcarrier lost - Demod.state = DEMOD_UNSYNCD; - } - } else { - Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF; - } - break; - - case DEMOD_AWAITING_FALLING_EDGE_OF_SOF: - - MAKE_SOFT_DECISION() - - //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq ); - // logic '0' detected - if (v <= 0) { - - Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF; - - // start of SOF sequence - Demod.posCount = 0; - } else { - // maximum length of TR1 = 200 1/fs - if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD; - } - ++Demod.posCount; - break; - - case DEMOD_GOT_FALLING_EDGE_OF_SOF: - ++Demod.posCount; - - MAKE_SOFT_DECISION() - - if(v > 0) { - // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges - if(Demod.posCount < 10*2) { - Demod.state = DEMOD_UNSYNCD; - } else { - LED_C_ON(); // Got SOF - Demod.state = DEMOD_AWAITING_START_BIT; - Demod.posCount = 0; - Demod.len = 0; - } - } else { - // low phase of SOF too long (> 12 etu) - if(Demod.posCount > 13*2) { - Demod.state = DEMOD_UNSYNCD; - LED_C_OFF(); - } - } - break; - - case DEMOD_AWAITING_START_BIT: - ++Demod.posCount; - - MAKE_SOFT_DECISION() - - if(v > 0) { - // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs - if(Demod.posCount > 3*2) { - Demod.state = DEMOD_UNSYNCD; - LED_C_OFF(); - } - } else { - // start bit detected - Demod.bitCount = 0; - Demod.posCount = 1; // this was the first half - Demod.thisBit = v; - Demod.shiftReg = 0; - Demod.state = DEMOD_RECEIVING_DATA; - } - break; - - case DEMOD_RECEIVING_DATA: - - MAKE_SOFT_DECISION() - - if(Demod.posCount == 0) { - // first half of bit - Demod.thisBit = v; - Demod.posCount = 1; - } else { - // second half of bit - Demod.thisBit += v; - Demod.shiftReg >>= 1; - // logic '1' - if(Demod.thisBit > 0) - Demod.shiftReg |= 0x200; - - ++Demod.bitCount; - - if(Demod.bitCount == 10) { - - uint16_t s = Demod.shiftReg; - - if((s & 0x200) && !(s & 0x001)) { - // stop bit == '1', start bit == '0' - uint8_t b = (s >> 1); - Demod.output[Demod.len] = b; - ++Demod.len; - Demod.state = DEMOD_AWAITING_START_BIT; - } else { - Demod.state = DEMOD_UNSYNCD; - LED_C_OFF(); - - if(s == 0x000) { - // This is EOF (start, stop and all data bits == '0' - return true; - } - } - } - Demod.posCount = 0; - } - break; - - default: - Demod.state = DEMOD_UNSYNCD; - LED_C_OFF(); - break; - } - return false; -} -*/ -/* -// Clear out the state of the "UART" that receives from the tag. -static void DemodReset() { - Demod.len = 0; - Demod.state = DEMOD_UNSYNCD; - Demod.posCount = 0; - Demod.sumI = 0; - Demod.sumQ = 0; - Demod.bitCount = 0; - Demod.thisBit = 0; - Demod.shiftReg = 0; - memset(Demod.output, 0x00, 3); } -static void DemodInit(uint8_t *data) { - Demod.output = data; - DemodReset(); -} -*/ - -/* - * Demodulate the samples we received from the tag, also log to tracebuffer - * quiet: set to 'TRUE' to disable debug output - */ - - /* - #define LEGIC_DMA_BUFFER_SIZE 256 - - static void GetSamplesForLegicDemod(int n, bool quiet) -{ - int max = 0; - bool gotFrame = false; - int lastRxCounter = LEGIC_DMA_BUFFER_SIZE; - int ci, cq, samples = 0; - - BigBuf_free(); - - // And put the FPGA in the appropriate mode - FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ); - - // The response (tag -> reader) that we're receiving. - // Set up the demodulator for tag -> reader responses. - DemodInit(BigBuf_malloc(MAX_FRAME_SIZE)); - - // The DMA buffer, used to stream samples from the FPGA - int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE); - int8_t *upTo = dmaBuf; - - // Setup and start DMA. - if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){ - if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting"); - return; - } - - // Signal field is ON with the appropriate LED: - LED_D_ON(); - for(;;) { - int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR; - if(behindBy > max) max = behindBy; - - while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) { - ci = upTo[0]; - cq = upTo[1]; - upTo += 2; - if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) { - upTo = dmaBuf; - AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; - AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE; - } - lastRxCounter -= 2; - if(lastRxCounter <= 0) - lastRxCounter = LEGIC_DMA_BUFFER_SIZE; - - samples += 2; - - gotFrame = HandleLegicSamplesDemod(ci , cq ); - if ( gotFrame ) - break; - } - - if(samples > n || gotFrame) - break; - } - - FpgaDisableSscDma(); - - if (!quiet && Demod.len == 0) { - Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", - max, - samples, - gotFrame, - Demod.len, - Demod.sumI, - Demod.sumQ - ); - } - - //Tracing - if (Demod.len > 0) { - uint8_t parity[MAX_PARITY_SIZE] = {0x00}; - LogTrace(Demod.output, Demod.len, 0, 0, parity, false); - } -} - -*/ - -//----------------------------------------------------------------------------- -// Transmit the command (to the tag) that was placed in ToSend[]. -//----------------------------------------------------------------------------- -/* -static void TransmitForLegic(void) -{ - int c; - - FpgaSetupSsc(); - - while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) - AT91C_BASE_SSC->SSC_THR = 0xff; - - // Signal field is ON with the appropriate Red LED - LED_D_ON(); - - // Signal we are transmitting with the Green LED - LED_B_ON(); - FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); - - for(c = 0; c < 10;) { - if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { - AT91C_BASE_SSC->SSC_THR = 0xff; - c++; - } - if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { - volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; - (void)r; - } - WDT_HIT(); - } - - c = 0; - for(;;) { - if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { - AT91C_BASE_SSC->SSC_THR = ToSend[c]; - legic_prng_forward(1); // forward the lfsr - c++; - if(c >= ToSendMax) { - break; - } - } - if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { - volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; - (void)r; - } - WDT_HIT(); - } - LED_B_OFF(); -} -*/ - -//----------------------------------------------------------------------------- -// Code a layer 2 command (string of octets, including CRC) into ToSend[], -// so that it is ready to transmit to the tag using TransmitForLegic(). -//----------------------------------------------------------------------------- -/* -static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) -{ - int i, j; - uint8_t b; - - ToSendReset(); - - // Send SOF - for(i = 0; i < 7; i++) - ToSendStuffBit(1); - - - for(i = 0; i < cmdlen; i++) { - // Start bit - ToSendStuffBit(0); - - // Data bits - b = cmd[i]; - for(j = 0; j < bits; j++) { - if(b & 1) { - ToSendStuffBit(1); - } else { - ToSendStuffBit(0); - } - b >>= 1; - } - } - - // Convert from last character reference to length - ++ToSendMax; -} -*/ -/** - Convenience function to encode, transmit and trace Legic comms - **/ -/* - static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) -{ - CodeLegicBitsAsReader(cmd, cmdlen, bits); - TransmitForLegic(); - if (tracing) { - uint8_t parity[1] = {0x00}; - LogTrace(cmd, cmdlen, 0, 0, parity, true); - } -} - -*/ -// Set up LEGIC communication -/* -void ice_legic_setup() { - - // standard things. - FpgaDownloadAndGo(FPGA_BITSTREAM_HF); - BigBuf_free(); BigBuf_Clear_ext(false); - clear_trace(); - set_tracing(true); - DemodReset(); - UartReset(); - - // Set up the synchronous serial port - FpgaSetupSsc(); - - // connect Demodulated Signal to ADC: - SetAdcMuxFor(GPIO_MUXSEL_HIPKD); - - // Signal field is on with the appropriate LED - LED_D_ON(); - FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); - SpinDelay(20); - // Start the timer - //StartCountSspClk(); - - // initalize CRC - crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); - - // initalize prng - legic_prng_init(0); -} -*/ \ No newline at end of file +} \ No newline at end of file