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CHG: the call to TurnReadLFOn has a delay / number as parameter. Seems to be gone.
FIX: fixes to EM4050 code since when I changed the timer. It should work nice now.
This commit is contained in:
iceman1001
parent
5b9fb6f454
commit
8ddfbc34dc
2 changed files with 25 additions and 27 deletions
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@ -94,7 +94,7 @@ void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t PwdMode
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void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t PwdMode);
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void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd);
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void T55xxWakeUp(uint32_t Pwd);
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void TurnReadLFOn();
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void TurnReadLFOn(uint32_t delay);
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void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode);
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void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode);
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@ -1116,10 +1116,10 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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* Q5 tags seems to have issues when these values changes.
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*/
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#define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
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#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
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#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
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#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
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#define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
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#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
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#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
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#define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
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#define READ_GAP 15*8
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// VALUES TAKEN FROM EM4x function: SendForward
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@ -1128,7 +1128,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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// WRITE_1 = 256 32*8; (32*8)
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// These timings work for 4469/4269/4305 (with the 55*8 above)
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// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
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// WRITE_0 = 23*8 , 9*8
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// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
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// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
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@ -1136,7 +1136,10 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
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// T0 = TIMER_CLOCK1 / 125000 = 192
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// 1 Cycle = 8 microseconds(us) == 1 field clock
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void TurnReadLFOn(int delay) {
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// new timer:
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// = 1us = 1.5ticks
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// 1fc = 8us = 12ticks
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void TurnReadLFOn(uint32_t delay) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// measure antenna strength.
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@ -1221,10 +1224,11 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
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// Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
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// so wait a little more)
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TurnReadLFOn(20 * 1000);
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//could attempt to do a read to confirm write took
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// as the tag should repeat back the new block
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// until it is reset, but to confirm it we would
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// need to know the current block 0 config mode
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//could attempt to do a read to confirm write took
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// as the tag should repeat back the new block
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// until it is reset, but to confirm it we would
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// need to know the current block 0 config mode
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// turn field off
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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@ -1513,9 +1517,9 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
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//-----------------------------------
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// EM4469 / EM4305 routines
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//-----------------------------------
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#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
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#define FWD_CMD_WRITE 0xA
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#define FWD_CMD_READ 0x9
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#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
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#define FWD_CMD_WRITE 0xA
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#define FWD_CMD_READ 0x9
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#define FWD_CMD_DISABLE 0x5
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uint8_t forwardLink_data[64]; //array of forwarded bits
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@ -1534,7 +1538,7 @@ uint8_t * fwd_write_ptr; //forwardlink bit pointer
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// WRITE_1 = 256 32*8; (32*8)
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// These timings work for 4469/4269/4305 (with the 55*8 above)
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// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
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// WRITE_0 = 23*8 , 9*8
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uint8_t Prepare_Cmd( uint8_t cmd ) {
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@ -1639,9 +1643,9 @@ void SendForward(uint8_t fwd_bit_count) {
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else {
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//These timings work for 4469/4269/4305 (with the 55*8 above)
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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WaitUS(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
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WaitUS(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
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}
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}
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}
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@ -1649,22 +1653,20 @@ void SendForward(uint8_t fwd_bit_count) {
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void EM4xLogin(uint32_t Password) {
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uint8_t fwd_bit_count;
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forward_ptr = forwardLink_data;
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fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
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fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
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SendForward(fwd_bit_count);
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//Wait for command to complete
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SpinDelay(20);
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WaitMS(20);
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}
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void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
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uint8_t fwd_bit_count;
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uint8_t *dest = BigBuf_get_addr();
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uint16_t bufsize = BigBuf_max_traceLen();
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uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
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uint32_t i = 0;
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// Clear destination buffer before sending the command
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@ -1677,14 +1679,10 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
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fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
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fwd_bit_count += Prepare_Addr( Address );
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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SendForward(fwd_bit_count);
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// Now do the acquisition
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// ICEMAN, change to the one in lfsampling.c
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i = 0;
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for(;;) {
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if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
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@ -1717,7 +1715,7 @@ void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode
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SendForward(fwd_bit_count);
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//Wait for write to complete
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SpinDelay(20);
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WaitMS(20);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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LED_D_OFF();
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}
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