mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 15:26:13 +08:00
fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.
This commit is contained in:
iceman1001
parent
e6c046e17c
commit
8df14408b8
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@ -5,17 +5,22 @@ RMDIR = rm -rf
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# rmdir only if dir is empty, tolerate failure
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RMDIR_SOFT = -rmdir
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#
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all: fpga_lf.bit fpga_hf.bit
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all: fpga_lf.bit fpga_hf.bit fpga_felica.bit
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clean:
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$(Q)$(RM) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
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$(Q)$(RM) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp xst_felica.srp
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$(Q)$(RM) *.map *.ngc *.xrpt *.pcf *.rbt *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst
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$(Q)$(RMDIR) *_auto_* xst
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v hi_sniffer.v hi_flite.v hi_get_trace.v
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#fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_flite.v hi_get_trace.v
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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$(Q)$(RM) $@
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$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
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fpga_felica.ngc: fpga_felica.v fpga.ucf xst_felica.scr util.v hi_simulate.v hi_reader.v hi_sniffer.v hi_flite.v hi_get_trace.v
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$(Q)$(RM) $@
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$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_felica.scr
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fpga_lf.ngc: fpga_lf.v fpga.ucf xst_lf.scr util.v clk_divider.v lo_edge_detect.v lo_read.v lo_passthru.v lp20khz_1MSa_iir_filter.v min_max_tracker.v lf_edge_detect.v
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$(Q)$(RM) $@
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172
fpga/fpga_hf.v
172
fpga/fpga_hf.v
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@ -23,23 +23,28 @@
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`define FPGA_CMD_TRACE_ENABLE 2
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// Major modes:
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`define FPGA_MAJOR_MODE_HF_READER_TX 0
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`define FPGA_MAJOR_MODE_HF_READER_RX_XCORR 1
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 2
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`define FPGA_MAJOR_MODE_HF_ISO14443A 3
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`define FPGA_MAJOR_MODE_HF_SNOOP 4
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`define FPGA_MAJOR_MODE_HF_ISO18092 5
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 6
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`define FPGA_MAJOR_MODE_HF_READER 0
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`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
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`define FPGA_MAJOR_MODE_HF_ISO14443A 2
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`define FPGA_MAJOR_MODE_HF_SNOOP 3
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`define FPGA_MAJOR_MODE_HF_ISO18092 4
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`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
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`define FPGA_MAJOR_MODE_OFF 7
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// Options for the generic HF reader
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// Options for the HF reader, tx to tag
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`define FPGA_HF_READER_TX_SHALLOW_MOD 1
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`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
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`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
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`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
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`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
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`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
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`define FPGA_HF_READER_MODE_SNIFF_IQ 5
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`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
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`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
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`define FPGA_HF_READER_MODE_SEND_JAM 8
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// Options for the HF reader, correlating against rx from tag
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`define FPGA_HF_READER_RX_XCORR_848_KHZ 1
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`define FPGA_HF_READER_RX_XCORR_SNOOP 2
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`define FPGA_HF_READER_RX_XCORR_QUARTER 4
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`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
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`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
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`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
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// Options for the HF simulated tag, how to modulate
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`define FPGA_HF_SIMULATOR_NO_MODULATION 0
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@ -60,13 +65,12 @@
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`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
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`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
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`include "hi_read_tx.v"
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`include "hi_read_rx_xcorr.v"
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`include "hi_reader.v"
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`include "hi_simulate.v"
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`include "hi_iso14443a.v"
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`include "hi_sniffer.v"
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`include "util.v"
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`include "hi_flite.v"
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// `include "hi_flite.v"
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`include "hi_get_trace.v"
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module fpga_hf(
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@ -105,14 +109,14 @@ bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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-----+-------------------------------------------
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cmd | x x x x
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major| x x x
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opt | x x
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opt | x x x
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divi | x x x x x x x x
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thres| x x x x x x x x
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-----+-------------------------------------------
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*/
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reg [15:0] shift_reg;
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reg [7:0] conf_word;
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reg [8:0] conf_word;
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reg trace_enable;
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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@ -121,7 +125,7 @@ reg trace_enable;
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always @(posedge ncs)
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begin
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case(shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[7:0];
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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endcase
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end
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@ -135,25 +139,12 @@ begin
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end
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end
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wire [2:0] major_mode = conf_word[7:5];
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// For the high-frequency transmit configuration: modulation depth, either
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// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
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// some fraction of the buffers)
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wire hi_read_tx_shallow_modulation = conf_word[0];
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// For the high-frequency receive correlator: frequency against which to
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// correlate.
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wire hi_read_rx_xcorr_848 = conf_word[0];
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// and whether to drive the coil (reader) or just short it (snooper)
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wire hi_read_rx_xcorr_snoop = conf_word[1];
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// divide subcarrier frequency by 4
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wire hi_read_rx_xcorr_quarter = conf_word[2];
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// For the high-frequency simulated tag: what kind of modulation to use.
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wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[5:4];
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wire [3:0] minor_mode = conf_word[3:0];
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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@ -161,95 +152,86 @@ wire [2:0] hi_simulate_mod_type = conf_word[2:0];
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// the output pins.
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//-----------------------------------------------------------------------------
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hi_read_tx ht(
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pck0, ck_1356meg, ck_1356megb,
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ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
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adc_d, ht_adc_clk,
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ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
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cross_hi, cross_lo,
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ht_dbg,
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hi_read_tx_shallow_modulation
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);
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hi_read_rx_xcorr hrxc(
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pck0, ck_1356meg, ck_1356megb,
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hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
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adc_d, hrxc_adc_clk,
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hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
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cross_hi, cross_lo,
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hrxc_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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// 000 - HF reader
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hi_reader hr(
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ck_1356megb,
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hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
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adc_d, hr_adc_clk,
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hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
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hr_dbg,
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subcarrier_frequency, minor_mode
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);
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// 001 - HF simulated tag
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hi_simulate hs(
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pck0, ck_1356meg, ck_1356megb,
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ck_1356meg,
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hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
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adc_d, hs_adc_clk,
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hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
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cross_hi, cross_lo,
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hs_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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// 010 - HF ISO14443-A
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hi_iso14443a hisn(
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pck0, ck_1356meg, ck_1356megb,
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ck_1356meg,
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hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
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adc_d, hisn_adc_clk,
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hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
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cross_hi, cross_lo,
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hisn_dbg,
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hi_simulate_mod_type
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minor_mode
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);
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// 011 - HF sniff
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hi_sniffer he(
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pck0, ck_1356meg, ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
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cross_hi, cross_lo,
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he_dbg,
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hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
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ck_1356megb,
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he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
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adc_d, he_adc_clk,
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he_ssp_frame, he_ssp_din, he_ssp_clk
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);
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// 100 - HF ISO18092 FeliCa
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/*
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hi_flite hfl(
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pck0, ck_1356meg, ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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cross_hi, cross_lo,
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hfl_dbg,
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hi_simulate_mod_type
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ck_1356megb,
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hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
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adc_d, hfl_adc_clk,
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hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
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hfl_dbg,
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minor_mode
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);
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*/
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// 101 - HF get trace
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hi_get_trace gt(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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gt_ssp_frame, gt_ssp_din, gt_ssp_clk
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);
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// Major modes:
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// 000 -- HF reader; subcarrier frequency and modulation depth selectable
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// 001 -- HF simulated tag
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// 010 -- HF ISO14443-A
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// 011 -- HF sniff
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// 100 -- HF ISO18092 FeliCa
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// 101 -- HF get trace
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// 110 -- unused
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// 111 -- FPGA_MAJOR_MODE_OFF
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// 000 -- HF reader, transmitting to tag; modulation depth selectable
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// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
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// 010 -- HF simulated tag
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// 011 -- HF ISO14443-A
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// 100 -- HF Snoop
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// 101 -- Felica modem, reusing HF reader
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// 110 -- HF get trace
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// 111 -- everything off
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// 000 001 010 011 100 101 110 111
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mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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@ -122,7 +122,7 @@ reg [7:0] divisor;
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reg [7:0] lf_ed_threshold;
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reg [11:0] conf_word;
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wire [2:0] major_mode = conf_word[7:5];
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wire [2:0] major_mode = conf_word[8:6];
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1];
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@ -135,7 +135,7 @@ begin
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begin
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||||
// 12 bit data
|
||||
conf_word <= shift_reg[11:0];
|
||||
if (shift_reg[7:5] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
|
||||
if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
|
||||
begin
|
||||
lf_ed_threshold <= 127; // default threshold
|
||||
end
|
||||
|
|
|
|||
|
|
@ -14,25 +14,23 @@
|
|||
*/
|
||||
|
||||
module hi_flite(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
mod_type
|
||||
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input [2:0] mod_type;
|
||||
assign dbg=0;
|
||||
input [3:0] mod_type;
|
||||
|
||||
assign dbg = 0;
|
||||
|
||||
wire power = mod_type[2];
|
||||
wire speed = mod_type[1];
|
||||
|
|
@ -40,7 +38,7 @@ wire disabl = mod_type[0];
|
|||
|
||||
// Most off, oe4 for modulation;
|
||||
// Trying reader emulation (would presumably just require switching power on, but I am not sure)
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_lo = 1'b0;
|
||||
|
||||
// 512x64/fc -wait before ts0, 32768 ticks
|
||||
// tslot: 256*64/fc
|
||||
|
|
@ -347,11 +345,11 @@ reg pwr_oe4;
|
|||
|
||||
wire mod = ((fccount >= bithalf) ^ dlay) & (~disabl);
|
||||
|
||||
always @(ck_1356megb or ssp_dout or power or disabl or mod)
|
||||
always @(ck_1356meg or ssp_dout or power or disabl or mod)
|
||||
begin
|
||||
if (power)
|
||||
begin
|
||||
pwr_hi <= ck_1356megb;
|
||||
pwr_hi <= ck_1356meg;
|
||||
pwr_oe1 <= 1'b0;//mod;
|
||||
pwr_oe2 <= 1'b0;//mod;
|
||||
pwr_oe3 <= 1'b0;//mod;
|
||||
|
|
|
|||
|
|
@ -3,31 +3,22 @@
|
|||
// Gerhard de Koning Gans, April 2008
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// constants for the different modes:
|
||||
`define SNIFFER 3'b000
|
||||
`define TAGSIM_LISTEN 3'b001
|
||||
`define TAGSIM_MOD 3'b010
|
||||
`define READER_LISTEN 3'b011
|
||||
`define READER_MOD 3'b100
|
||||
|
||||
module hi_iso14443a(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
mod_type
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input [2:0] mod_type;
|
||||
input [3:0] mod_type;
|
||||
|
||||
|
||||
wire adc_clk = ck_1356meg;
|
||||
|
|
@ -151,7 +142,7 @@ begin
|
|||
end
|
||||
|
||||
// adjust internal timer counter if necessary:
|
||||
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
|
||||
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation)
|
||||
begin
|
||||
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
|
||||
begin
|
||||
|
|
@ -185,7 +176,7 @@ reg [3:0] mod_detect_reset_time;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (mod_type == `READER_LISTEN)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
|
||||
// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
|
||||
// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
|
||||
// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
|
||||
|
|
@ -195,7 +186,7 @@ begin
|
|||
mod_detect_reset_time <= 4'd4;
|
||||
end
|
||||
else
|
||||
if (mod_type == `SNIFFER)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
|
||||
if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
|
||||
|
|
@ -320,7 +311,7 @@ reg [3:0] sub_carrier_cnt;
|
|||
// response window of 1128 - 774 = 354 ticks.
|
||||
|
||||
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
|
||||
assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
|
||||
assign fdt_reset = ~after_hysteresis && mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
|
|
@ -363,7 +354,7 @@ reg mod_sig_coil;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (mod_type == `TAGSIM_MOD) // need to take care of proper fdt timing
|
||||
if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) // need to take care of proper fdt timing
|
||||
begin
|
||||
if(fdt_counter == `FDT_COUNT)
|
||||
begin
|
||||
|
|
@ -438,7 +429,7 @@ always @(negedge adc_clk)
|
|||
begin
|
||||
if (negedge_cnt[5:0] == 6'd63) // fill the buffer
|
||||
begin
|
||||
if (mod_type == `SNIFFER)
|
||||
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
if(deep_modulation) // a reader is sending (or there's no field at all)
|
||||
begin
|
||||
|
|
@ -455,7 +446,7 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER) // shift at double speed
|
||||
if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER) // shift at double speed
|
||||
begin
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if(negedge_cnt[5:0] != 6'd0)
|
||||
|
|
@ -464,7 +455,7 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
|
||||
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER)
|
||||
begin
|
||||
// Don't shift if we just loaded new data, obviously.
|
||||
if(negedge_cnt[6:0] != 7'd0)
|
||||
|
|
@ -484,8 +475,8 @@ reg ssp_frame;
|
|||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(mod_type == `SNIFFER)
|
||||
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
||||
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
// FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
|
||||
begin
|
||||
if(negedge_cnt[2:0] == 3'd0)
|
||||
ssp_clk <= 1'b1;
|
||||
|
|
@ -505,7 +496,7 @@ begin
|
|||
if(negedge_cnt[3:0] == 4'd8)
|
||||
ssp_clk <= 1'b0;
|
||||
|
||||
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame
|
||||
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk
|
||||
ssp_frame <= 1'b1;
|
||||
if(negedge_cnt[6:0] == 7'd23)
|
||||
ssp_frame <= 1'b0;
|
||||
|
|
@ -525,23 +516,23 @@ begin
|
|||
if(negedge_cnt[3:0] == 4'd0)
|
||||
begin
|
||||
// What do we communicate to the ARM
|
||||
if(mod_type == `TAGSIM_LISTEN)
|
||||
if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN)
|
||||
sendbit = after_hysteresis;
|
||||
else if(mod_type == `TAGSIM_MOD)
|
||||
else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)
|
||||
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
|
||||
else */
|
||||
sendbit = fdt_indicator;
|
||||
else if (mod_type == `READER_LISTEN)
|
||||
else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
|
||||
sendbit = curbit;
|
||||
else
|
||||
sendbit = 1'b0;
|
||||
end
|
||||
|
||||
|
||||
if(mod_type == `SNIFFER)
|
||||
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
|
||||
// send sampled reader and tag data:
|
||||
bit_to_arm = to_arm[7];
|
||||
else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
|
||||
else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
|
||||
// send timing information:
|
||||
bit_to_arm = to_arm[7];
|
||||
else
|
||||
|
|
@ -554,22 +545,22 @@ end
|
|||
|
||||
assign ssp_din = bit_to_arm;
|
||||
|
||||
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
|
||||
// Subcarrier (adc_clk/16, for FPGA_HF_ISO14443A_TAGSIM_MOD only).
|
||||
wire sub_carrier;
|
||||
assign sub_carrier = ~sub_carrier_cnt[3];
|
||||
|
||||
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
|
||||
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
|
||||
// in FPGA_HF_ISO14443A_READER_MOD: drop carrier for mod_sig_coil==1 (pause); in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
|
||||
assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
|
||||
|
||||
|
||||
// Enable HF antenna drivers:
|
||||
assign pwr_oe1 = 1'b0;
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
|
||||
// FPGA_HF_ISO14443A_TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
|
||||
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
|
||||
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
|
||||
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD);
|
||||
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD);
|
||||
|
||||
// This is all LF, so doesn't matter.
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
|
|
|||
|
|
@ -17,82 +17,105 @@
|
|||
//-----------------------------------------------------------------------------
|
||||
|
||||
module hi_simulate(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
mod_type
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input [2:0] mod_type;
|
||||
input [3:0] mod_type;
|
||||
|
||||
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
|
||||
// always be low.
|
||||
assign pwr_hi = 1'b0;
|
||||
assign pwr_lo = 1'b0;
|
||||
assign pwr_hi = 1'b0; // HF antenna connected to GND
|
||||
assign pwr_lo = 1'b0; // LF antenna connected to GND
|
||||
|
||||
// This one is all LF, so doesn't matter
|
||||
assign pwr_oe2 = 1'b0;
|
||||
|
||||
assign adc_clk = ck_1356meg;
|
||||
assign dbg = ssp_frame;
|
||||
|
||||
// The comparator with hysteresis on the output from the peak detector.
|
||||
reg after_hysteresis;
|
||||
assign adc_clk = ck_1356meg;
|
||||
reg [11:0] has_been_low_for;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(& adc_d[7:5]) after_hysteresis = 1'b1;
|
||||
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
|
||||
if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
|
||||
else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
|
||||
|
||||
if (adc_d >= 224)
|
||||
begin
|
||||
has_been_low_for <= 12'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (has_been_low_for == 12'd4095)
|
||||
begin
|
||||
has_been_low_for <= 12'd0;
|
||||
after_hysteresis <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
has_been_low_for <= has_been_low_for + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Divide 13.56 MHz to produce various frequencies for SSP_CLK
|
||||
// and modulation. 11 bits allow for factors of up to /128.
|
||||
reg [10:0] ssp_clk_divider;
|
||||
// and modulation.
|
||||
reg [8:0] ssp_clk_divider;
|
||||
|
||||
always @(posedge adc_clk)
|
||||
always @(negedge adc_clk)
|
||||
ssp_clk_divider <= (ssp_clk_divider + 1);
|
||||
|
||||
reg ssp_clk;
|
||||
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if(mod_type == 3'b101)
|
||||
// Get bit every at 53kHz (every 8th carrier bit of 424kHz)
|
||||
ssp_clk <= ssp_clk_divider[7];
|
||||
else if(mod_type == 3'b010)
|
||||
if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
|
||||
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
|
||||
ssp_clk <= ~ssp_clk_divider[7];
|
||||
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
|
||||
// Get next bit at 212kHz
|
||||
ssp_clk <= ssp_clk_divider[5];
|
||||
ssp_clk <= ~ssp_clk_divider[5];
|
||||
else
|
||||
// Get next bit at 424kHz
|
||||
ssp_clk <= ssp_clk_divider[4];
|
||||
ssp_clk <= ~ssp_clk_divider[4];
|
||||
end
|
||||
|
||||
|
||||
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
|
||||
// this is arbitrary, because it's just a bitstream.
|
||||
// One nasty issue, though: I can't make it work with both rx and tx at
|
||||
// once. The phase wrt ssp_clk must be changed. TODO to find out why
|
||||
// that is and make a better fix.
|
||||
reg [2:0] ssp_frame_divider_to_arm;
|
||||
always @(posedge ssp_clk)
|
||||
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
|
||||
reg [2:0] ssp_frame_divider_from_arm;
|
||||
always @(negedge ssp_clk)
|
||||
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
|
||||
|
||||
|
||||
// Produce the byte framing signal; the phase of this signal
|
||||
// is arbitrary, because it's just a bit stream in this module.
|
||||
reg ssp_frame;
|
||||
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
|
||||
if(mod_type == 3'b000) // not modulating, so listening, to ARM
|
||||
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
|
||||
always @(negedge adc_clk)
|
||||
begin
|
||||
if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
|
||||
begin
|
||||
if (ssp_clk_divider[8:5] == 4'd1)
|
||||
ssp_frame <= 1'b1;
|
||||
if (ssp_clk_divider[8:5] == 4'd5)
|
||||
ssp_frame <= 1'b0;
|
||||
end
|
||||
else
|
||||
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
|
||||
begin
|
||||
if (ssp_clk_divider[7:4] == 4'd1)
|
||||
ssp_frame <= 1'b1;
|
||||
if (ssp_clk_divider[7:4] == 4'd5)
|
||||
ssp_frame <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Synchronize up the after-hysteresis signal, to produce DIN.
|
||||
reg ssp_din;
|
||||
|
|
@ -101,29 +124,25 @@ always @(posedge ssp_clk)
|
|||
|
||||
// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
|
||||
reg modulating_carrier;
|
||||
always @(mod_type or ssp_clk or ssp_dout)
|
||||
if(mod_type == 3'b000)
|
||||
always @(*)
|
||||
if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
|
||||
modulating_carrier <= 1'b0; // no modulation
|
||||
else if(mod_type == 3'b001)
|
||||
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
|
||||
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
|
||||
else if(mod_type == 3'b010)
|
||||
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
|
||||
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
|
||||
else if(mod_type == 3'b100 || mod_type == 3'b101)
|
||||
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
|
||||
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
|
||||
else
|
||||
modulating_carrier <= 1'b0; // yet unused
|
||||
|
||||
// This one is all LF, so doesn't matter
|
||||
assign pwr_oe2 = modulating_carrier;
|
||||
|
||||
// Toggle only one of these, since we are already producing much deeper
|
||||
|
||||
// Load modulation. Toggle only one of these, since we are already producing much deeper
|
||||
// modulation than a real tag would.
|
||||
assign pwr_oe1 = modulating_carrier;
|
||||
assign pwr_oe4 = modulating_carrier;
|
||||
|
||||
assign pwr_oe1 = 1'b0; // 33 Ohms Load
|
||||
assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
|
||||
// This one is always on, so that we can watch the carrier.
|
||||
assign pwr_oe3 = 1'b0;
|
||||
|
||||
assign dbg = ssp_din;
|
||||
assign pwr_oe3 = 1'b0; // 10k Load
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,21 +1,14 @@
|
|||
module hi_sniffer(
|
||||
pck0, ck_1356meg, ck_1356megb,
|
||||
ck_1356meg,
|
||||
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
|
||||
adc_d, adc_clk,
|
||||
ssp_frame, ssp_din, ssp_dout, ssp_clk,
|
||||
cross_hi, cross_lo,
|
||||
dbg,
|
||||
xcorr_is_848, snoop, xcorr_quarter_freq // not used.
|
||||
ssp_frame, ssp_din, ssp_clk
|
||||
);
|
||||
input pck0, ck_1356meg, ck_1356megb;
|
||||
input ck_1356meg;
|
||||
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
|
||||
input [7:0] adc_d;
|
||||
output adc_clk;
|
||||
input ssp_dout;
|
||||
output ssp_frame, ssp_din, ssp_clk;
|
||||
input cross_hi, cross_lo;
|
||||
output dbg;
|
||||
input xcorr_is_848, snoop, xcorr_quarter_freq; // not used.
|
||||
|
||||
// We are only snooping, all off.
|
||||
assign pwr_hi = 1'b0;
|
||||
|
|
|
|||
Loading…
Reference in a new issue