This version code now reads a TI tag properly.

armsrc/appmain.c

@@ -206,23 +206,22 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
 	DoAcquisition125k(at134khz);
 }
 
-//-----------------------------------------------------------------------------
-// Read a TI-type tag. We assume that the tag has already been illuminated,
-// and that the exciting signal has been turned off. That means that we just
-// acquire the `one-bit DAC' bits from the comparator.
-//-----------------------------------------------------------------------------
 void AcquireTiType(void)
 {
 	int i;
-	int n = sizeof(BigBuf);
+	int n = 5000;
 
 	// clear buffer
 	memset(BigBuf,0,sizeof(BigBuf));
 
-  // Set up the synchronous serial port
+	// Set up the synchronous serial port
   PIO_DISABLE = (1<<GPIO_SSC_DIN);
   PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);
 
+	// steal this pin from the SSP and use it to control the modulation
+  PIO_ENABLE = (1<<GPIO_SSC_DOUT);
+	PIO_OUTPUT_ENABLE	= (1<<GPIO_SSC_DOUT);
+
   SSC_CONTROL = SSC_CONTROL_RESET;
   SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
 
@@ -231,18 +230,35 @@ void AcquireTiType(void)
   SSC_CLOCK_DIVISOR = 12;
 
   SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);
-  SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
-  SSC_TRANSMIT_CLOCK_MODE = 0;
-  SSC_TRANSMIT_FRAME_MODE = 0;
+	SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
+	SSC_TRANSMIT_CLOCK_MODE = 0;
+	SSC_TRANSMIT_FRAME_MODE = 0;
 
-  i = 0;
-  for(;;) {
-      if(SSC_STATUS & SSC_STATUS_RX_READY) {
-          BigBuf[i] = SSC_RECEIVE_HOLDING;	// store 32 bit values in buffer
-          i++; if(i >= n) return;
-      }
-      WDT_HIT();
-  }
+	LED_D_ON();
+
+	// modulate antenna
+	PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
+
+	// Charge TI tag for 50ms.
+	SpinDelay(50);
+
+	// stop modulating antenna and listen
+	PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
+
+	LED_D_OFF();
+
+	i = 0;
+	for(;;) {
+			if(SSC_STATUS & SSC_STATUS_RX_READY) {
+					BigBuf[i] = SSC_RECEIVE_HOLDING;	// store 32 bit values in buffer
+					i++; if(i >= n) return;
+			}
+			WDT_HIT();
+	}
+
+	// return stolen pin ro SSP
+	PIO_DISABLE = (1<<GPIO_SSC_DOUT);
+	PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);
 }
 
 void AcquireRawBitsTI(void)
@@ -250,22 +266,16 @@ void AcquireRawBitsTI(void)
 	LED_D_ON();
 	// TI tags charge at 134.2Khz
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-
-	// Charge TI tag for 50ms.
-	SpinDelay(50);
-	LED_D_OFF();
-
-	LED_A_ON();
-	// Place FPGA in passthrough mode so as to stop driving the LF coil,
-	// in this mode the CROSS_LO line connects to SSP_DIN
+	// Place FPGA in passthrough mode, in this mode the CROSS_LO line
+	// connects to SSP_DIN and the SSP_DOUT logic level controls
+	// whether we're modulating the antenna (high)
+	// or listening to the antenna (low)
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 
 	// get TI tag data into the buffer
 	AcquireTiType();
 
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	LED_A_OFF();
 }
 
 //-----------------------------------------------------------------------------

fpga/fpga.v

@@ -129,7 +129,7 @@ lo_passthru lp(
 	adc_d, lp_adc_clk,
 	lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
 	cross_hi, cross_lo,
-	lp_dbg
+	lp_dbg, divisor
 );
 
 lo_simulate ls(

fpga/lo_passthru.v

@@ -9,7 +9,7 @@ module lo_passthru(
     adc_d, adc_clk,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
-    dbg
+    dbg, divisor
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -19,14 +19,35 @@ module lo_passthru(
     output ssp_frame, ssp_din, ssp_clk;
     input cross_hi, cross_lo;
     output dbg;
+    input [7:0] divisor;
 
-// No logic, straight through.
+reg [7:0] pck_divider;
+reg ant_lo;
 
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
+// which is high for (divisor+1) pck0 cycles and low for the same duration
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
+always @(posedge pck0)
+begin
+	if(pck_divider == divisor[7:0])
+		begin
+			pck_divider <= 8'd0;
+			ant_lo = !ant_lo;
+		end
+	else
+	begin
+		pck_divider <= pck_divider + 1;
+	end
+end
+
+// the antenna is modulated when ssp_dout = 1, when 0 the
+// antenna drivers stop modulating and go into listen mode
 assign pwr_oe3 = 1'b0;
-assign pwr_oe1 = 1'b1;
-assign pwr_oe2 = 1'b1;
-assign pwr_oe4 = 1'b1;
-assign pwr_lo = 1'b0;
+assign pwr_oe1 = ssp_dout;
+assign pwr_oe2 = ssp_dout;
+assign pwr_oe4 = ssp_dout;
+assign pwr_lo = ant_lo && ssp_dout;
 assign pwr_hi = 1'b0;
 assign adc_clk = 1'b0;
 assign ssp_din = cross_lo;