RfidResearchGroup/proxmark3
1
1
Fork 0
mirror of https://github.com/RfidResearchGroup/proxmark3.git synced 2025-01-31 12:31:32 +08:00
Code Issues Projects Releases Packages Wiki Activity

fix: wrong define

Browse source
This commit is contained in:
iceman1001 2018-02-21 09:03:02 +01:00
parent 6a374988ba
commit 92a42c2189
1 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
armsrc/flashmem.c
View file

@ -5,7 +5,7 @@
/* here: use NCPS2 @ PA10: */ /* here: use NCPS2 @ PA10: */
#define NCPS_PDR_BIT AT91C_PA10_NPCS2 // GPIO #define NCPS_PDR_BIT AT91C_PA10_NPCS2 // GPIO
#define NCPS_ASR_BIT 0 // SPI peripheral A #define NCPS_ASR_BIT 0 // SPI peripheral A
#define NPCS_BSR_BIT AT91C_PA10_NPCS2 // SPI peripheral B #define NCPS_BSR_BIT AT91C_PA10_NPCS2 // SPI peripheral B
#define SPI_CSR_NUM 2 // Chip Select register[] 0,1,2,3 (at91samv512 has 4) #define SPI_CSR_NUM 2 // Chip Select register[] 0,1,2,3 (at91samv512 has 4)
/* PCS_0 for NPCS0, PCS_1 for NPCS1 ... */ /* PCS_0 for NPCS0, PCS_1 for NPCS1 ... */
@ -52,12 +52,12 @@ void FlashSetup(void) {
//AT91C_BASE_PIOA->PIO_PER = GPIO_NCS1 | GPIO_MOSI | GPIO_SPCK | GPIO_MISO; //AT91C_BASE_PIOA->PIO_PER = GPIO_NCS1 | GPIO_MOSI | GPIO_SPCK | GPIO_MISO;
// Disable PIO control of the following pins, hand over to SPI control // Disable PIO control of the following pins, hand over to SPI control
AT91C_BASE_PIOA->PIO_PDR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK; AT91C_BASE_PIOA->PIO_PDR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_PDR_BIT;
// Peripheral A // Peripheral A
AT91C_BASE_PIOA->PIO_ASR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK; AT91C_BASE_PIOA->PIO_ASR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_ASR_BIT;
// Peripheral B // Peripheral B
AT91C_BASE_PIOA->PIO_BSR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK; AT91C_BASE_PIOA->PIO_BSR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_BSR_BIT ;
// set chip-select as output high (unselect card) // set chip-select as output high (unselect card)
AT91C_BASE_PIOA->PIO_PER = NCPS_PDR_BIT; // enable GPIO of CS-pin AT91C_BASE_PIOA->PIO_PER = NCPS_PDR_BIT; // enable GPIO of CS-pin
@ -110,7 +110,7 @@ void FlashSetup(void) {
AT91C_BASE_PIOA->PIO_PDR |= NCPS_PDR_BIT; AT91C_BASE_PIOA->PIO_PDR |= NCPS_PDR_BIT;
// set pin-functions in PIO Controller (function NCPS for CS-pin) // set pin-functions in PIO Controller (function NCPS for CS-pin)
AT91C_BASE_PIOA->PIO_ASR |= NCPS_ASR_BIT; AT91C_BASE_PIOA->PIO_ASR |= NCPS_ASR_BIT;
AT91C_BASE_PIOA->PIO_BSR |= NPCS_BSR_BIT; AT91C_BASE_PIOA->PIO_BSR |= NCPS_BSR_BIT;
} }
void FlashStop(void) { void FlashStop(void) {