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https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-03-20 12:07:05 +08:00
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commit
94ad01bfba
4 changed files with 43 additions and 33 deletions
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@ -100,6 +100,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
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#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
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// Options for ISO14443A
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#define FPGA_HF_ISO14443A_SNIFFER (0<<0)
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#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
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@ -1090,6 +1090,12 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
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CodeIClassTagAnswer(response4, sizeof(response4));
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memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax;
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// Start from off (no field generated)
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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SpinDelay(200);
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// We need to listen to the high-frequency, peak-detected path.
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaSetupSsc();
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@ -1107,11 +1113,17 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
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displayDebug = true;
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LED_B_OFF();
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//Signal tracer
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// Can be used to get a trigger for an oscilloscope..
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LED_C_OFF();
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if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
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buttonPressed = true;
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break;
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}
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r2t_time = GetCountSspClk();
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//Signal tracer
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LED_C_ON();
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// Okay, look at the command now.
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if(receivedCmd[0] == 0x0a ) {
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@ -1236,41 +1248,34 @@ int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived)
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static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
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{
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int i = 0, u = 0, d = 0;
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int i = 0, d=0;//, u = 0, d = 0;
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uint8_t b = 0;
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// return 0;
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// Modulate Manchester
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// FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD424);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
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AT91C_BASE_SSC->SSC_THR = 0x00;
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FpgaSetupSsc();
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// send cycle
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for(;;) {
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
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(void)b;
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while(!BUTTON_PRESS()) {
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if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
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b = AT91C_BASE_SSC->SSC_RHR; (void) b;
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}
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
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b = 0x00;
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if(d < delay) {
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b = 0x00;
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d++;
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}
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else if(i >= respLen) {
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b = 0x00;
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u++;
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} else {
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b = resp[i];
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u++;
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if(u > 1) { i++; u = 0; }
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else {
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if( i < respLen){
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b = resp[i];
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//Hack
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//b = 0xAC;
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}
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i++;
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}
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AT91C_BASE_SSC->SSC_THR = b;
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}
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if(u > 4) break;
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}
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if(BUTTON_PRESS()) {
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break;
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}
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if (i > respLen +4) break;
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}
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return 0;
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@ -1284,7 +1289,6 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
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static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
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{
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int c;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
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AT91C_BASE_SSC->SSC_THR = 0x00;
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FpgaSetupSsc();
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@ -1360,12 +1364,12 @@ void CodeIClassCommand(const uint8_t * cmd, int len)
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b = cmd[i];
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for(j = 0; j < 4; j++) {
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for(k = 0; k < 4; k++) {
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if(k == (b & 3)) {
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ToSend[++ToSendMax] = 0x0f;
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}
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else {
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ToSend[++ToSendMax] = 0x00;
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}
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if(k == (b & 3)) {
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ToSend[++ToSendMax] = 0x0f;
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}
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else {
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ToSend[++ToSendMax] = 0x00;
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}
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}
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b >>= 2;
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}
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BIN
fpga/fpga.bit
BIN
fpga/fpga.bit
Binary file not shown.
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@ -89,7 +89,9 @@ always @(mod_type or ssp_clk or ssp_dout)
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else if(mod_type == 3'b001)
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modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
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else if(mod_type == 3'b010)
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modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
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modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
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else if(mod_type == 3'b100)
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modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
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else
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modulating_carrier <= 1'b0; // yet unused
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@ -105,5 +107,8 @@ assign pwr_oe4 = modulating_carrier;
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assign pwr_oe3 = 1'b0;
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assign dbg = after_hysteresis;
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//reg dbg;
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//always @(ssp_dout)
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// dbg <= ssp_dout;
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endmodule
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