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https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 15:26:13 +08:00
send sync signal to clock when reset
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9ec32e1fe8
commit
b993236be2
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@ -1148,6 +1148,9 @@ void SniffHitag2(void) {
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// Enable and reset counter
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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// Assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1;
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int frame_count = 0, response = 0, overflow = 0, lastbit = 1, tag_sof = 4;
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bool rising_edge = false, reader_frame = false, bSkip = true;
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uint8_t rx[HITAG_FRAME_LEN];
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@ -1293,11 +1296,15 @@ void SniffHitag2(void) {
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// Reset the timer to restart while-loop that receives frames
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
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// Assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1;
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}
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LEDsoff();
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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set_tracing(false);
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@ -246,6 +246,9 @@ void lf_init(bool reader, bool simulate) {
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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// Assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1;
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// Prepare data trace
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uint32_t bufsize = 10000;
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@ -14,13 +14,17 @@
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#define ALLOC 16
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size_t DemodPCF7931(uint8_t **outBlocks) {
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// 2021 iceman, memor
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uint8_t bits[256] = {0x00};
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uint8_t blocks[8][16];
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uint8_t *dest = BigBuf_get_addr();
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int GraphTraceLen = BigBuf_max_traceLen();
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if (GraphTraceLen > 18000)
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if (GraphTraceLen > 18000) {
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GraphTraceLen = 18000;
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}
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int i = 2, j, lastval, bitidx, half_switch;
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int clock = 64;
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@ -38,15 +42,17 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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/* Find first local max/min */
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if (dest[1] > dest[0]) {
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while (i < GraphTraceLen) {
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if (!(dest[i] > dest[i - 1]) && dest[i] > lmax)
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if (!(dest[i] > dest[i - 1]) && dest[i] > lmax) {
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break;
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}
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i++;
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}
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dir = 0;
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} else {
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while (i < GraphTraceLen) {
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if (!(dest[i] < dest[i - 1]) && dest[i] < lmin)
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if (!(dest[i] < dest[i - 1]) && dest[i] < lmin) {
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break;
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}
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i++;
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}
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dir = 1;
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@ -58,6 +64,7 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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block_done = 0;
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for (bitidx = 0; i < GraphTraceLen; i++) {
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if ((dest[i - 1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i - 1] < dest[i] && dir == 0 && dest[i] < lmin)) {
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lc = i - lastval;
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lastval = i;
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@ -66,8 +73,8 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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// Tolerance is 1/8 of clock rate (arbitrary)
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if (ABS(lc - clock / 4) < tolerance) {
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// 16T0
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if ((i - pmc) == lc) { /* 16T0 was previous one */
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/* It's a PMC ! */
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if ((i - pmc) == lc) { // 16T0 was previous one
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// It's a PMC
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i += (128 + 127 + 16 + 32 + 33 + 16) - 1;
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lastval = i;
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pmc = 0;
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@ -77,8 +84,8 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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}
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} else if (ABS(lc - clock / 2) < tolerance) {
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// 32TO
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if ((i - pmc) == lc) { /* 16T0 was previous one */
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/* It's a PMC ! */
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if ((i - pmc) == lc) { // 16T0 was previous one
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// It's a PMC !
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i += (128 + 127 + 16 + 32 + 33) - 1;
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lastval = i;
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pmc = 0;
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@ -95,8 +102,9 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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// Error
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if (++warnings > 10) {
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if (DBGLEVEL >= DBG_EXTENDED)
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Dbprintf("Error: too many detection errors, aborting.");
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if (DBGLEVEL >= DBG_EXTENDED) {
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Dbprintf("Error: too many detection errors, aborting");
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}
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return 0;
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}
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@ -122,13 +130,19 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
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block_done = 0;
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half_switch = 0;
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}
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if (i < GraphTraceLen)
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if (i < GraphTraceLen) {
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dir = (dest[i - 1] > dest[i]) ? 0 : 1;
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}
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}
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if (bitidx == 255)
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if (bitidx == 255) {
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bitidx = 0;
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warnings = 0;
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if (num_blocks == 4) break;
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}
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if (num_blocks == 4) {
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break;
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}
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}
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memcpy(outBlocks, blocks, 16 * num_blocks);
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return num_blocks;
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@ -138,10 +152,11 @@ bool IsBlock0PCF7931(uint8_t *block) {
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// assuming all RFU bits are set to 0
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// if PAC is enabled password is set to 0
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if (block[7] == 0x01) {
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if (!memcmp(block, "\x00\x00\x00\x00\x00\x00\x00", 7)
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&& !memcmp(block + 9, "\x00\x00\x00\x00\x00\x00\x00", 7)) {
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if (!memcmp(block, "\x00\x00\x00\x00\x00\x00\x00", 7) &&
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!memcmp(block + 9, "\x00\x00\x00\x00\x00\x00\x00", 7)) {
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return true;
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}
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} else if (block[7] == 0x00) {
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if (!memcmp(block + 9, "\x00\x00\x00\x00\x00\x00\x00", 7)) {
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return true;
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@ -158,14 +173,14 @@ bool IsBlock1PCF7931(uint8_t *block) {
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uint8_t rlb = block[15];
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if (block[10] == 0
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&& block[11] == 0
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&& block[12] == 0
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&& block[13] == 0) {
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&& block[11] == 0
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&& block[12] == 0
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&& block[13] == 0) {
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// block 1 is sent only if (RLB >= 1 && RFB <= 1) or RB1 enabled
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if (rfb <= rlb
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&& rfb <= 9
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&& rlb <= 9
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&& ((rfb <= 1 && rlb >= 1) || rb1)) {
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&& rfb <= 9
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&& rlb <= 9
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&& ((rfb <= 1 && rlb >= 1) || rb1)) {
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return true;
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}
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}
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@ -211,8 +226,9 @@ void ReadPCF7931(void) {
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// exit if too many errors during reading
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if (tries > 50 && (2 * errors > tries)) {
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if (DBGLEVEL >= DBG_INFO)
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if (DBGLEVEL >= DBG_INFO) {
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Dbprintf("[!!] Error reading the tag, only partial content");
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}
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goto end;
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}
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@ -461,27 +477,32 @@ void SendCmdPCF7931(uint32_t *tab) {
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//initialization of the timer
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AT91C_BASE_PMC->PMC_PCER |= (0x1 << AT91C_ID_TC0);
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; //clock at 48/32 MHz
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; // clock at 48/32 MHz
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
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// Assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1;
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tempo = AT91C_BASE_TC0->TC_CV;
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for (u = 0; tab[u] != 0; u += 3) {
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// modulate antenna
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HIGH(GPIO_SSC_DOUT);
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while (tempo != tab[u])
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while (tempo != tab[u]) {
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tempo = AT91C_BASE_TC0->TC_CV;
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}
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// stop modulating antenna
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LOW(GPIO_SSC_DOUT);
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while (tempo != tab[u + 1])
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while (tempo != tab[u + 1]) {
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tempo = AT91C_BASE_TC0->TC_CV;
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}
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// modulate antenna
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HIGH(GPIO_SSC_DOUT);
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while (tempo != tab[u + 2])
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while (tempo != tab[u + 2]) {
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tempo = AT91C_BASE_TC0->TC_CV;
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}
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}
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LED_A_OFF();
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@ -125,6 +125,8 @@ void StartCountUS(void) {
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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// Assert a sync signal. This sets all timers to 0 on next active clock edge
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AT91C_BASE_TCB->TCB_BCR = 1;
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while (AT91C_BASE_TC1->TC_CV > 0);
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