diff --git a/fpga/fpga_hf.bit b/fpga/fpga_hf.bit
index 50128bbe7..f74ca9236 100644
Binary files a/fpga/fpga_hf.bit and b/fpga/fpga_hf.bit differ
diff --git a/fpga/fpga_lf.bit b/fpga/fpga_lf.bit
index a4d0f85f7..89ed6ee03 100644
Binary files a/fpga/fpga_lf.bit and b/fpga/fpga_lf.bit differ
diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index fc309cde6..e4c433415 100644
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -12,7 +12,7 @@ module hi_read_tx(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,
-    shallow_modulation
+    shallow_modulation, speed, power
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -23,6 +23,8 @@ module hi_read_tx(
     input cross_hi, cross_lo;
     output dbg;
     input shallow_modulation;
+    input [1:0] speed;
+    input power;
 
 // low frequency outputs, not relevant
 assign pwr_lo = 1'b0;
@@ -36,6 +38,8 @@ reg pwr_oe3;
 reg pwr_oe4;
 
 always @(ck_1356megb or ssp_dout or shallow_modulation)
+begin
+if (power)
 begin
     if(shallow_modulation)
     begin
@@ -52,6 +56,14 @@ begin
         pwr_oe4 <= 1'b0;
     end
 end
+else
+begin
+       pwr_hi <= 1'b0;
+        pwr_oe1 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= ~ssp_dout;
+end    
+end
 
 
 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
@@ -62,7 +74,7 @@ reg [6:0] hi_div_by_128;
 always @(posedge ck_1356meg)
     hi_div_by_128 <= hi_div_by_128 + 1;
 
-assign ssp_clk = hi_div_by_128[6];
+assign ssp_clk = speed[1]? (speed[0]? hi_div_by_128[3]: hi_div_by_128[4]) : (speed[0]? hi_div_by_128[5]: hi_div_by_128[6]);
 
 reg [2:0] hi_byte_div;