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Initial attempt at TI tag reading.

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This commit is contained in:
d18c7db 2009-07-19 04:37:07 +00:00
parent 17465c9edd
commit c701d2c2fa
1 changed files with 104 additions and 38 deletions
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84
armsrc/appmain.c
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@ -103,10 +103,10 @@ void AcquireRawAdcSamples125k(BOOL at134khz)
{
if(at134khz) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
} else {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
}
// Connect the A/D to the peak-detected low-frequency path.
@ -160,10 +160,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
if(at134khz) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
} else {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
}
// Give it a bit of time for the resonant antenna to settle.
@ -180,10 +180,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
SpinDelayUs(delay_off);
if(at134khz) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
} else {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
}
LED_D_ON();
if(*(command++) == '0')
@ -196,16 +196,78 @@ void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYT
SpinDelayUs(delay_off);
if(at134khz) {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
} else {
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
}
// now do the read
DoAcquisition125k(at134khz);
}
//-----------------------------------------------------------------------------
// Read a TI-type tag. We assume that the tag has already been illuminated,
// and that the exciting signal has been turned off. That means that we just
// acquire the `one-bit DAC' bits from the comparator.
//-----------------------------------------------------------------------------
void AcquireTiType(void)
{
int i;
int n = 4000;
// clear buffer
memset(BigBuf,0,sizeof(BigBuf));
// Set up the synchronous serial port
PIO_DISABLE = (1<<GPIO_SSC_DIN);
PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);
SSC_CONTROL = SSC_CONTROL_RESET;
SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
// Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
// 48/2 = 24 MHz clock must be divided by 12
SSC_CLOCK_DIVISOR = 12;
SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);
SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
SSC_TRANSMIT_CLOCK_MODE = 0;
SSC_TRANSMIT_FRAME_MODE = 0;
i = 0;
for(;;) {
if(SSC_STATUS & SSC_STATUS_RX_READY) {
BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer
i++; if(i >= n) return;
}
WDT_HIT();
}
}
void AcquireRawBitsTI(void)
{
LED_D_ON();
// TI tags charge at 134.2Khz
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
// Charge TI tag for 50ms.
SpinDelay(50);
LED_D_OFF();
LED_A_ON();
// Place FPGA in passthrough mode so as to stop driving the LF coil,
// in this mode the CROSS_LO line connects to SSP_DIN
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
// get TI tag data into the buffer
AcquireTiType();
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_A_OFF();
}
//-----------------------------------------------------------------------------
// Read an ADC channel and block till it completes, then return the result
// in ADC units (0 to 1023). Also a routine to average 32 samples and
@ -452,7 +514,7 @@ static void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
DWORD hi=0, lo=0;
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
// Connect the A/D to the peak-detected low-frequency path.
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
@ -698,6 +760,10 @@ void UsbPacketReceived(BYTE *packet, int len)
ModThenAcquireRawAdcSamples125k(c->ext1,c->ext2,c->ext3,c->d.asBytes);
break;
case CMD_ACQUIRE_RAW_BITS_TI_TYPE:
AcquireRawBitsTI();
break;
case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693:
AcquireRawAdcSamplesIso15693();
break;