mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2024-09-20 15:26:13 +08:00
Avoid hardcoded lf divisors
This commit is contained in:
parent
b993819b92
commit
cce039554d
|
@ -738,7 +738,7 @@ void SniffHitag(void) {
|
|||
// Set up eavesdropping mode, frequency divisor which will drive the FPGA
|
||||
// and analog mux selection.
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125);
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Configure output pin that is connected to the FPGA (for modulating)
|
||||
|
@ -967,7 +967,7 @@ void SimulateHitagTag(bool tag_mem_supplied, uint8_t *data) {
|
|||
// Set up simulator mode, frequency divisor which will drive the FPGA
|
||||
// and analog mux selection.
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Configure output pin that is connected to the FPGA (for modulating)
|
||||
|
@ -1173,7 +1173,7 @@ void ReaderHitag(hitag_function htf, hitag_data *htd) {
|
|||
|
||||
// Set fpga in edge detect with reader field, we can modulate as reader now
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Configure output and enable pin that is connected to the FPGA (for modulating)
|
||||
|
@ -1444,7 +1444,7 @@ void WriterHitag(hitag_function htf, hitag_data *htd, int page) {
|
|||
|
||||
// Set fpga in edge detect with reader field, we can modulate as reader now
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Disable modulation at default, which means enable the field
|
||||
|
|
|
@ -994,7 +994,7 @@ void SimulateHitagSTag(bool tag_mem_supplied, uint8_t *data) {
|
|||
// and analog mux selection.
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Configure output pin that is connected to the FPGA (for modulating)
|
||||
|
@ -1193,7 +1193,7 @@ void ReadHitagS(hitag_function htf, hitag_data *htd) {
|
|||
|
||||
// Set fpga in edge detect with reader field, we can modulate as reader now
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Configure output and enable pin that is connected to the FPGA (for modulating)
|
||||
|
@ -1528,7 +1528,7 @@ void WritePageHitagS(hitag_function htf, hitag_data *htd, int page) {
|
|||
|
||||
// Set fpga in edge detect with reader field, we can modulate as reader now
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Disable modulation at default, which means enable the field
|
||||
|
@ -1789,7 +1789,7 @@ void check_challenges(bool file_given, uint8_t *data) {
|
|||
|
||||
// Set fpga in edge detect with reader field, we can modulate as reader now
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
|
||||
|
||||
// Disable modulation at default, which means enable the field
|
||||
|
|
|
@ -503,7 +503,7 @@ void ReadTItag(void) {
|
|||
|
||||
// TI tags charge at 134.2kHz
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
|
||||
|
||||
// Place FPGA in passthrough mode, in this mode the CROSS_LO line
|
||||
// connects to SSP_DIN and the SSP_DOUT logic level controls
|
||||
|
@ -730,7 +730,7 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) {
|
|||
Dbprintf("Writing to tag: %x%08x, crc=%x", idhi, idlo, crc);
|
||||
|
||||
// TI tags charge at 134.2kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
|
||||
// Place FPGA in passthrough mode, in this mode the CROSS_LO line
|
||||
// connects to SSP_DIN and the SSP_DOUT logic level controls
|
||||
// whether we're modulating the antenna (high)
|
||||
|
@ -803,9 +803,9 @@ void SimulateTagLowFrequencyEx(int period, int gap, bool ledcontrol, int numcycl
|
|||
sample_config *sc = getSamplingConfig();
|
||||
|
||||
if ((sc->divisor == 1) || (sc->divisor < 0) || (sc->divisor > 255))
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
|
||||
else if (sc->divisor == 0)
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
else
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
|
||||
|
||||
|
@ -1145,7 +1145,7 @@ void CmdHIDdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol)
|
|||
uint32_t hi2 = 0, hi = 0, lo = 0;
|
||||
int dummyIdx = 0;
|
||||
// Configure to go in 125kHz listen mode
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
//clear read buffer
|
||||
BigBuf_Clear_keep_EM();
|
||||
|
@ -1242,7 +1242,7 @@ void CmdAWIDdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol)
|
|||
|
||||
BigBuf_Clear_keep_EM();
|
||||
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
while (!BUTTON_PRESS() && !data_available()) {
|
||||
|
||||
|
@ -1334,7 +1334,7 @@ void CmdEM410xdemod(int findone, uint32_t *high, uint64_t *low, int ledcontrol)
|
|||
|
||||
BigBuf_Clear_keep_EM();
|
||||
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
while (!BUTTON_PRESS() && !data_available()) {
|
||||
|
||||
|
@ -1400,7 +1400,7 @@ void CmdIOdemodFSK(int findone, uint32_t *high, uint32_t *low, int ledcontrol) {
|
|||
BigBuf_Clear_keep_EM();
|
||||
|
||||
// Configure to go in 125kHz listen mode
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
while (!BUTTON_PRESS() && !data_available()) {
|
||||
WDT_HIT();
|
||||
|
@ -1651,7 +1651,7 @@ void T55xx_SendCMD(uint32_t data, uint32_t pwd, uint16_t arg) {
|
|||
|
||||
// Send Bits to T55xx
|
||||
// Set up FPGA, 125kHz
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
// make sure tag is fully powered up...
|
||||
WaitMS(start_wait);
|
||||
|
@ -2274,7 +2274,7 @@ void SendForward(uint8_t fwd_bit_count) {
|
|||
fwd_bit_sz = fwd_bit_count;
|
||||
|
||||
// Set up FPGA, 125kHz or 95 divisor
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
|
||||
// force 1st mod pulse (start gap must be longer for 4305)
|
||||
fwd_bit_sz--; //prepare next bit modulation
|
||||
|
@ -2396,7 +2396,7 @@ void Cotag(uint32_t arg0) {
|
|||
|
||||
LED_A_ON();
|
||||
|
||||
LFSetupFPGAForADC(89, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_134, true);
|
||||
|
||||
//clear buffer now so it does not interfere with timing later
|
||||
BigBuf_Clear_ext(false);
|
||||
|
|
|
@ -95,9 +95,9 @@ void pushBit(BitstreamOut *stream, uint8_t bit) {
|
|||
void LFSetupFPGAForADC(int divisor, bool lf_field) {
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
||||
if ((divisor == 1) || (divisor < 0) || (divisor > 255))
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_134); //~134kHz
|
||||
else if (divisor == 0)
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
else
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
|
||||
|
||||
|
|
|
@ -32,7 +32,7 @@ size_t DemodPCF7931(uint8_t **outBlocks) {
|
|||
uint8_t dir;
|
||||
|
||||
BigBuf_Clear_keep_EM();
|
||||
LFSetupFPGAForADC(95, true);
|
||||
LFSetupFPGAForADC(LF_DIVISOR_125, true);
|
||||
DoAcquisition_default(0, true);
|
||||
|
||||
/* Find first local max/min */
|
||||
|
@ -449,7 +449,7 @@ void SendCmdPCF7931(uint32_t *tab) {
|
|||
}
|
||||
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125kHz
|
||||
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, LF_DIVISOR_125); //125kHz
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
|
||||
|
||||
LED_A_ON();
|
||||
|
|
Loading…
Reference in a new issue