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CHG: Added the BigBuf_Clear_ext calls, returned to Marshmellow42 's / pwpiwi 's sampledemod. The 14B commands works again...

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CHG: re-arranged the Uart, Demod structes init, reset,   in a first attempt to prepair to move them to a seperate file.
This commit is contained in:
iceman1001 2016-03-13 07:20:21 +01:00
parent ef8e50c64b
commit cef590d9ef
1 changed files with 257 additions and 229 deletions
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486
armsrc/iso14443b.c
View file

@ -15,10 +15,9 @@
#include "string.h"
#include "iso14443crc.h"
#include "common.h"
#define RECEIVE_SAMPLES_TIMEOUT 600000
#define RECEIVE_SAMPLES_TIMEOUT 20000
#define ISO14443B_DMA_BUFFER_SIZE 256
// PCB Block number for APDUs
static uint8_t pcb_blocknum = 0;
@ -30,6 +29,88 @@ static uint8_t pcb_blocknum = 0;
// a response.
//=============================================================================
//-----------------------------------------------------------------------------
// The software UART that receives commands from the reader, and its state
// variables.
//-----------------------------------------------------------------------------
static struct {
enum {
STATE_UNSYNCD,
STATE_GOT_FALLING_EDGE_OF_SOF,
STATE_AWAITING_START_BIT,
STATE_RECEIVING_DATA
} state;
uint16_t shiftReg;
int bitCnt;
int byteCnt;
int byteCntMax;
int posCnt;
uint8_t *output;
} Uart;
static void UartReset()
{
Uart.byteCntMax = MAX_FRAME_SIZE;
Uart.state = STATE_UNSYNCD;
Uart.byteCnt = 0;
Uart.bitCnt = 0;
Uart.posCnt = 0;
memset(Uart.output, 0x00, MAX_FRAME_SIZE);
}
static void UartInit(uint8_t *data)
{
Uart.output = data;
UartReset();
}
static struct {
enum {
DEMOD_UNSYNCD,
DEMOD_PHASE_REF_TRAINING,
DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
DEMOD_GOT_FALLING_EDGE_OF_SOF,
DEMOD_AWAITING_START_BIT,
DEMOD_RECEIVING_DATA
} state;
int bitCount;
int posCount;
int thisBit;
/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
int metric;
int metricN;
*/
uint16_t shiftReg;
uint8_t *output;
int len;
int sumI;
int sumQ;
} Demod;
static void DemodReset()
{
// Clear out the state of the "UART" that receives from the tag.
Demod.len = 0;
Demod.state = DEMOD_UNSYNCD;
Demod.posCount = 0;
Demod.sumI = 0;
Demod.sumQ = 0;
Demod.bitCount = 0;
Demod.thisBit = 0;
Demod.shiftReg = 0;
memset(Demod.output, 0x00, MAX_FRAME_SIZE);
}
static void DemodInit(uint8_t *data)
{
Demod.output = data;
DemodReset();
}
//-----------------------------------------------------------------------------
// Code up a string of octets at layer 2 (including CRC, we don't generate
// that here) so that they can be transmitted to the reader. Doesn't transmit
@ -117,24 +198,7 @@ static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
ToSendMax++;
}
//-----------------------------------------------------------------------------
// The software UART that receives commands from the reader, and its state
// variables.
//-----------------------------------------------------------------------------
static struct {
enum {
STATE_UNSYNCD,
STATE_GOT_FALLING_EDGE_OF_SOF,
STATE_AWAITING_START_BIT,
STATE_RECEIVING_DATA
} state;
uint16_t shiftReg;
int bitCnt;
int byteCnt;
int byteCntMax;
int posCnt;
uint8_t *output;
} Uart;
/* Receive & handle a bit coming from the reader.
*
@ -262,25 +326,6 @@ static RAMFUNC int Handle14443bUartBit(uint8_t bit)
return FALSE;
}
static void UartReset()
{
Uart.byteCntMax = MAX_FRAME_SIZE;
Uart.state = STATE_UNSYNCD;
Uart.byteCnt = 0;
Uart.bitCnt = 0;
Uart.posCnt = 0;
memset(Uart.output, 0x00, MAX_FRAME_SIZE);
}
static void UartInit(uint8_t *data)
{
Uart.output = data;
UartReset();
}
//-----------------------------------------------------------------------------
// Receive a command (from the reader to us, where we are the simulated tag),
// and store it in the given buffer, up to the given maximum length. Keeps
@ -345,7 +390,7 @@ void SimulateIso14443bTag(void)
// response to HLTB and ATTRIB
static const uint8_t response2[] = {0x00, 0x78, 0xF0};
uint8_t parity[MAX_PARITY_SIZE] = {0x00};
//uint8_t parity[MAX_PARITY_SIZE] = {0x00};
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
@ -357,7 +402,8 @@ void SimulateIso14443bTag(void)
uint16_t respLen, respCodeLen;
// allocate command receive buffer
BigBuf_free();
BigBuf_free(); BigBuf_Clear_ext(false);
uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
uint16_t len;
@ -388,7 +434,10 @@ void SimulateIso14443bTag(void)
break;
}
LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
if (tracing)
//LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
// Good, look at the command now.
if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
@ -442,41 +491,30 @@ void SimulateIso14443bTag(void)
AT91C_BASE_SSC->SSC_THR = 0xff;
FpgaSetupSsc();
uint8_t c;
// clear receiving shift register and holding register
while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
c = AT91C_BASE_SSC->SSC_RHR; (void) c;
while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
c = AT91C_BASE_SSC->SSC_RHR; (void) c;
// Clear TXRDY:
AT91C_BASE_SSC->SSC_THR = 0x00;
// Transmit the response.
uint16_t FpgaSendQueueDelay = 0;
uint16_t i = 0;
for(;i < respCodeLen; ) {
for(;;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = respCode[i++];
FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
}
if(BUTTON_PRESS()) break;
}
// Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0x00;
FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
uint8_t b = respCode[i];
AT91C_BASE_SSC->SSC_THR = b;
i++;
if(i > respCodeLen) {
break;
}
}
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
(void)b;
}
}
LogTrace(resp, respLen, 0, 0, parity, FALSE);
// trace the response:
if (tracing)
//LogTrace(resp, respLen, 0, 0, parity, FALSE);
LogTrace(resp, respLen, 0, 0, NULL, FALSE);
}
FpgaDisableSscDma();
set_tracing(FALSE);
}
//=============================================================================
@ -486,29 +524,6 @@ void SimulateIso14443bTag(void)
// PC side.
//=============================================================================
static struct {
enum {
DEMOD_UNSYNCD,
DEMOD_PHASE_REF_TRAINING,
DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
DEMOD_GOT_FALLING_EDGE_OF_SOF,
DEMOD_AWAITING_START_BIT,
DEMOD_RECEIVING_DATA
} state;
int bitCount;
int posCount;
int thisBit;
/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
int metric;
int metricN;
*/
uint16_t shiftReg;
uint8_t *output;
int len;
int sumI;
int sumQ;
} Demod;
/*
* Handles reception of a bit from the tag
*
@ -523,15 +538,13 @@ static struct {
* false if we are still waiting for some more
*
*/
#define abs(x) ( ((x)<0) ? -(x) : (x) )
#ifndef SUBCARRIER_DETECT_THRESHOLD
# define SUBCARRIER_DETECT_THRESHOLD 6
#endif
static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
{
int v = 0;
int ai = abs(ci);
int aq = abs(cq);
int halfci = (ai >> 1);
int halfcq = (aq >> 1);
// The soft decision on the bit uses an estimate of just the
// quadrant of the reference angle, not the exact angle.
#define MAKE_SOFT_DECISION() { \
@ -547,18 +560,58 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
} \
}
#define SUBCARRIER_DETECT_THRESHOLD 8
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
/* #define CHECK_FOR_SUBCARRIER() { \
v = ci; \
if(v < 0) v = -v; \
if(cq > 0) { \
v += cq; \
} else { \
v -= cq; \
} \
}
*/
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
#define CHECK_FOR_SUBCARRIER() { \
v = MAX(ai, aq) + MIN(halfci, halfcq); \
}
if(ci < 0) { \
if(cq < 0) { /* ci < 0, cq < 0 */ \
if (cq < ci) { \
v = -cq - (ci >> 1); \
} else { \
v = -ci - (cq >> 1); \
} \
} else { /* ci < 0, cq >= 0 */ \
if (cq < -ci) { \
v = -ci + (cq >> 1); \
} else { \
v = cq - (ci >> 1); \
} \
} \
} else { \
if(cq < 0) { /* ci >= 0, cq < 0 */ \
if (-cq < ci) { \
v = ci - (cq >> 1); \
} else { \
v = -cq + (ci >> 1); \
} \
} else { /* ci >= 0, cq >= 0 */ \
if (cq < ci) { \
v = ci + (cq >> 1); \
} else { \
v = cq + (ci >> 1); \
} \
} \
} \
}
switch(Demod.state) {
case DEMOD_UNSYNCD:
CHECK_FOR_SUBCARRIER();
if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
// subcarrier detected
if(v > SUBCARRIER_DETECT_THRESHOLD) {
Demod.state = DEMOD_PHASE_REF_TRAINING;
Demod.sumI = ci;
Demod.sumQ = cq;
@ -568,15 +621,17 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
case DEMOD_PHASE_REF_TRAINING:
if(Demod.posCount < 8) {
//if(Demod.posCount < 10*2) {
CHECK_FOR_SUBCARRIER();
if (v > SUBCARRIER_DETECT_THRESHOLD) {
// set the reference phase (will code a logic '1') by averaging over 32 1/fs.
// note: synchronization time > 80 1/fs
Demod.sumI += ci;
Demod.sumQ += cq;
Demod.posCount++;
} else { // subcarrier lost
++Demod.posCount;
} else {
// subcarrier lost
Demod.state = DEMOD_UNSYNCD;
}
} else {
@ -585,37 +640,38 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
break;
case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
MAKE_SOFT_DECISION();
//Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
if(v <= 0) { // logic '0' detected
if(v < 0) { // logic '0' detected
Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
Demod.posCount = 0; // start of SOF sequence
} else {
if(Demod.posCount > 25*2) { // maximum length of TR1 = 200 1/fs
Demod.state = DEMOD_UNSYNCD;
}
// maximum length of TR1 = 200 1/fs
if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
}
Demod.posCount++;
++Demod.posCount;
break;
case DEMOD_GOT_FALLING_EDGE_OF_SOF:
Demod.posCount++;
++Demod.posCount;
MAKE_SOFT_DECISION();
if(v > 0) {
if(Demod.posCount < 10*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
// low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
if(Demod.posCount < 9*2) {
Demod.state = DEMOD_UNSYNCD;
} else {
LED_C_ON(); // Got SOF
Demod.state = DEMOD_AWAITING_START_BIT;
Demod.posCount = 0;
Demod.len = 0;
/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
Demod.metricN = 0;
Demod.metric = 0;
*/
}
} else {
if(Demod.posCount > 13*2) { // low phase of SOF too long (> 12 etu)
// low phase of SOF too long (> 12 etu)
if (Demod.posCount > 12*2) {
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
}
@ -623,9 +679,11 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
break;
case DEMOD_AWAITING_START_BIT:
Demod.posCount++;
++Demod.posCount;
MAKE_SOFT_DECISION();
if(v > 0) {
if (v > 0) {
if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
@ -640,42 +698,39 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
break;
case DEMOD_RECEIVING_DATA:
MAKE_SOFT_DECISION();
if(Demod.posCount == 0) { // first half of bit
if (Demod.posCount == 0) {
// first half of bit
Demod.thisBit = v;
Demod.posCount = 1;
} else { // second half of bit
} else {
// second half of bit
Demod.thisBit += v;
/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
if(Demod.thisBit > 0) {
Demod.metric += Demod.thisBit;
} else {
Demod.metric -= Demod.thisBit;
}
(Demod.metricN)++;
*/
Demod.shiftReg >>= 1;
if(Demod.thisBit > 0) { // logic '1'
Demod.shiftReg |= 0x200;
}
Demod.bitCount++;
// logic '1'
if(Demod.thisBit > 0) Demod.shiftReg |= 0x200;
++Demod.bitCount;
if(Demod.bitCount == 10) {
uint16_t s = Demod.shiftReg;
if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
// stop bit == '1', start bit == '0'
if((s & 0x200) && !(s & 0x001)) {
uint8_t b = (s >> 1);
Demod.output[Demod.len] = b;
Demod.len++;
++Demod.len;
Demod.state = DEMOD_AWAITING_START_BIT;
} else {
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
if(s == 0x000) {
// This is EOF (start, stop and all data bits == '0'
return TRUE;
}
// This is EOF (start, stop and all data bits == '0'
if(s == 0) return TRUE;
}
}
Demod.posCount = 0;
@ -691,28 +746,6 @@ static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
}
static void DemodReset()
{
// Clear out the state of the "UART" that receives from the tag.
Demod.len = 0;
Demod.state = DEMOD_UNSYNCD;
Demod.posCount = 0;
Demod.sumI = 0;
Demod.sumQ = 0;
Demod.bitCount = 0;
Demod.thisBit = 0;
Demod.shiftReg = 0;
memset(Demod.output, 0x00, MAX_FRAME_SIZE);
}
static void DemodInit(uint8_t *data)
{
Demod.output = data;
DemodReset();
}
/*
* Demodulate the samples we received from the tag, also log to tracebuffer
* quiet: set to 'TRUE' to disable debug output
@ -727,9 +760,6 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
// free all previous allocations first
BigBuf_free();
// And put the FPGA in the appropriate mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
// The response (tag -> reader) that we're receiving.
// Set up the demodulator for tag -> reader responses.
DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
@ -737,6 +767,9 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
// The DMA buffer, used to stream samples from the FPGA
int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
// And put the FPGA in the appropriate mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
// Setup and start DMA.
FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
@ -759,9 +792,9 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
}
lastRxCounter -= 2;
if(lastRxCounter <= 0) {
lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
}
if(lastRxCounter <= 0)
lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
samples += 2;
@ -776,13 +809,15 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
}
}
//disable
AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
if (!quiet) {
Dbprintf("max behindby = %d, samples = %d, gotFrame = %s, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
Dbprintf("max behindby = %d, samples = %d, gotFrame = %s, Demod.state = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
max,
samples,
(gotFrame) ? "true" : "false",
Demod.state,
Demod.len,
Demod.sumI,
Demod.sumQ
@ -790,10 +825,8 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
}
//Tracing
if (Demod.len > 0) {
uint8_t parity[MAX_PARITY_SIZE] = {0x00};
LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
}
if (Demod.len > 0)
LogTrace(Demod.output, Demod.len, 0, 0, NULL, FALSE);
}
@ -803,12 +836,11 @@ static void GetSamplesFor14443bDemod(int n, bool quiet)
static void TransmitFor14443b(void)
{
int c;
volatile uint32_t r;
FpgaSetupSsc();
while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
AT91C_BASE_SSC->SSC_THR = 0xff;
}
// Signal field is ON with the appropriate Red LED
LED_D_ON();
@ -819,10 +851,10 @@ static void TransmitFor14443b(void)
for(c = 0; c < 10;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0xff;
c++;
++c;
}
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
r = AT91C_BASE_SSC->SSC_RHR;
(void)r;
}
WDT_HIT();
@ -832,13 +864,12 @@ static void TransmitFor14443b(void)
for(;;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = ToSend[c];
c++;
if(c >= ToSendMax) {
++c;
if(c >= ToSendMax)
break;
}
}
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
r = AT91C_BASE_SSC->SSC_RHR;
(void)r;
}
WDT_HIT();
@ -859,13 +890,12 @@ static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
ToSendReset();
// Establish initial reference level
for(i = 0; i < 40; i++) {
for(i = 0; i < 40; i++)
ToSendStuffBit(1);
}
// Send SOF
for(i = 0; i < 11; i++) {
for(i = 0; i < 10; i++)
ToSendStuffBit(0);
}
for(i = 0; i < len; i++) {
// Stop bits/EGT
@ -876,31 +906,30 @@ static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
// Data bits
b = cmd[i];
for(j = 0; j < 8; j++) {
if(b & 1) {
if(b & 1)
ToSendStuffBit(1);
} else {
else
ToSendStuffBit(0);
}
b >>= 1;
}
}
// Send EOF
ToSendStuffBit(1);
for(i = 0; i < 11; i++) {
for(i = 0; i < 10; i++)
ToSendStuffBit(0);
}
for(i = 0; i < 8; i++) {
for(i = 0; i < 8; i++)
ToSendStuffBit(1);
}
// And then a little more, to make sure that the last character makes
// it out before we switch to rx mode.
for(i = 0; i < 10; i++) {
for(i = 0; i < 24; i++)
ToSendStuffBit(1);
}
// Convert from last character reference to length
ToSendMax++;
++ToSendMax;
}
@ -912,8 +941,9 @@ static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
CodeIso14443bAsReader(cmd, len);
TransmitFor14443b();
if (tracing) {
uint8_t parity[MAX_PARITY_SIZE];
LogTrace(cmd,len, 0, 0, parity, TRUE);
//uint8_t parity[MAX_PARITY_SIZE];
//LogTrace(cmd,len, 0, 0, parity, TRUE);
LogTrace(cmd,len, 0, 0, NULL, TRUE);
}
}
@ -935,17 +965,15 @@ int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *respo
// send
CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
// get response
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT*100, TRUE);
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
if(Demod.len < 3)
{
return 0;
}
// TODO: Check CRC
// copy response contents
if(response != NULL)
{
memcpy(response, Demod.output, Demod.len);
}
return Demod.len;
}
@ -968,9 +996,7 @@ int iso14443b_select_card()
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
// ATQB too short?
if (Demod.len < 14)
{
return 2;
}
// select the tag
// copy the PUPI to ATTRIB
@ -983,9 +1009,8 @@ int iso14443b_select_card()
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
// Answer to ATTRIB too short?
if(Demod.len < 3)
{
return 2;
}
// reset PCB block number
pcb_blocknum = 0;
return 1;
@ -995,24 +1020,24 @@ int iso14443b_select_card()
void iso14443b_setup() {
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
BigBuf_free(); BigBuf_Clear_ext(false);
DemodReset();
UartReset();
BigBuf_free();
// Set up the synchronous serial port
FpgaSetupSsc();
// connect Demodulated Signal to ADC:
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
// Signal field is on with the appropriate LED
LED_D_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
//SpinDelay(100);
SpinDelay(200);
// Start the timer
StartCountSspClk();
DemodReset();
UartReset();
}
//-----------------------------------------------------------------------------
@ -1027,8 +1052,6 @@ void iso14443b_setup() {
void ReadSTMemoryIso14443b(uint32_t dwLast)
{
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
BigBuf_free();
clear_trace();
set_tracing(TRUE);
@ -1175,7 +1198,7 @@ void RAMFUNC SnoopIso14443b(void)
int triggered = TRUE; // TODO: set and evaluate trigger condition
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
BigBuf_free();
BigBuf_free(); BigBuf_Clear_ext(false);
clear_trace();
set_tracing(TRUE);
@ -1213,7 +1236,7 @@ void RAMFUNC SnoopIso14443b(void)
upTo = dmaBuf;
lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
uint8_t parity[MAX_PARITY_SIZE] = {0x00};
//uint8_t parity[MAX_PARITY_SIZE] = {0x00};
bool TagIsActive = FALSE;
bool ReaderIsActive = FALSE;
@ -1258,9 +1281,10 @@ void RAMFUNC SnoopIso14443b(void)
if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
if (Handle14443bUartBit(ci & 0x01)) {
if ( triggered)
LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
if(triggered && tracing) {
//LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, TRUE);
}
/* And ready to receive another command. */
UartReset();
/* And also reset the demod code, which might have been */
@ -1268,9 +1292,10 @@ void RAMFUNC SnoopIso14443b(void)
DemodReset();
}
if (Handle14443bUartBit(cq & 0x01)) {
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
if(triggered && tracing) {
//LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, TRUE);
}
/* And ready to receive another command. */
UartReset();
/* And also reset the demod code, which might have been */
@ -1282,10 +1307,12 @@ void RAMFUNC SnoopIso14443b(void)
if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
// is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
if(Handle14443bSamplesDemod(ci & 0xfe, cq & 0xfe)) {
if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
//Use samples as a time measurement
LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
if(tracing)
//LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
LogTrace(Demod.output, Demod.len, samples, samples, NULL, FALSE);
triggered = TRUE;
@ -1334,14 +1361,15 @@ void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, u
if ( datalen == 0 && recv == 0 && powerfield == 0){
} else {
clear_trace();
set_tracing(TRUE);
CodeAndTransmit14443bAsReader(data, datalen);
}
if (recv) {
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, FALSE);
uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
uint16_t len = MIN(Demod.len, USB_CMD_DATA_SIZE);
cmd_send(CMD_ACK, len, 0, 0, Demod.output, len);
}
if (!powerfield) {