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FPGA Hi-Simulate: Added 212kHz SSP-Clock option
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fpga/fpga_hf.bit
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fpga/fpga_hf.bit
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@ -65,9 +65,12 @@ begin
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if(mod_type == 3'b101)
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// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
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ssp_clk <= ssp_clk_divider[7];
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else if(mod_type == 3'b010)
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// Get next bit at 212kHz
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ssp_clk <= ssp_clk_divider[5];
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else
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// Get next bit at 424Khz
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ssp_clk <= ssp_clk_divider[4]
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ssp_clk <= ssp_clk_divider[4];
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end
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@ -121,6 +124,6 @@ assign pwr_oe4 = modulating_carrier;
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// This one is always on, so that we can watch the carrier.
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assign pwr_oe3 = 1'b0;
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assign dbg = modulating_carrier;
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assign dbg = ssp_din;
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endmodule
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