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Add HF simulator modulation mode for 212kHz subcarrier

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henryk@ploetzli.ch 2009-10-12 07:46:03 +00:00
parent 789d706a7d
commit ecf53cb215
3 changed files with 5 additions and 1 deletions
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1
armsrc/apps.h
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@ -56,6 +56,7 @@ void SetAdcMuxFor(DWORD whichGpio);
// Options for the HF simulated tag, how to modulate // Options for the HF simulated tag, how to modulate
#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
// Options for ISO14443A // Options for ISO14443A
#define FPGA_HF_ISO14443A_SNIFFER (0<<0) #define FPGA_HF_ISO14443A_SNIFFER (0<<0)
#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0) #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)

BIN
fpga/fpga.bit
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5
fpga/hi_simulate.v
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@ -51,7 +51,8 @@ begin
end end
// Divide 13.56 MHz by 32 to produce the SSP_CLK // Divide 13.56 MHz by 32 to produce the SSP_CLK
reg [4:0] ssp_clk_divider; // The register is bigger to allow higher division factors of up to /128
reg [6:0] ssp_clk_divider;
always @(posedge adc_clk) always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1); ssp_clk_divider <= (ssp_clk_divider + 1);
assign ssp_clk = ssp_clk_divider[4]; assign ssp_clk = ssp_clk_divider[4];
@ -87,6 +88,8 @@ always @(mod_type or ssp_clk or ssp_dout)
modulating_carrier <= 1'b0; // no modulation modulating_carrier <= 1'b0; // no modulation
else if(mod_type == 3'b001) else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else else
modulating_carrier <= 1'b0; // yet unused modulating_carrier <= 1'b0; // yet unused