chg: reverting old @satsuoni felica changes.

chg: applied @pwpiwi 's fixes for iso 14B / 15

fpga/hi_flite.v

@@ -392,10 +392,10 @@ always @(ck_1356megb or ssp_dout or power or disabl or mod)
 if (power)
            begin
         pwr_hi <= ck_1356megb;
-        pwr_oe1 <= mod;
-        pwr_oe2 <= mod;
-        pwr_oe3 <= mod;
-        pwr_oe4 <= 1'b0;
+        pwr_oe1 <= 1'b0;//mod;
+        pwr_oe2 <= 1'b0;//mod;
+        pwr_oe3 <= 1'b0;//mod;
+        pwr_oe4 <= mod;//1'b0;
            end
 else
           begin          

fpga/hi_read_rx_xcorr.v

@@ -34,13 +34,13 @@ always @(negedge ck_1356megb)
 
 (* clock_signal = "yes" *) reg adc_clk;				// sample frequency, always 16 * fc
 always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
-	if (xcorr_is_848 & ~xcorr_quarter_freq)			// fc = 847.5 kHz
+	if (xcorr_is_848 & ~xcorr_quarter_freq)			// fc = 847.5 kHz, standard ISO14443B
 		adc_clk <= ck_1356megb;
-	else if (~xcorr_is_848 & ~xcorr_quarter_freq)	// fc = 424.25 kHz 
+	else if (~xcorr_is_848 & ~xcorr_quarter_freq)	// fc = 423.75 kHz 
 		adc_clk <= fc_div[0];
-	else if (xcorr_is_848 & xcorr_quarter_freq)		// fc = 212.125 kHz
+	else if (xcorr_is_848 & xcorr_quarter_freq)		// fc = 211.875 kHz
 		adc_clk <= fc_div[1];
-	else 											// fc = 106.0625 kHz
+	else 											// fc = 105.9375 kHz
 		adc_clk <= fc_div[2];
 
 // When we're a reader, we just need to do the BPSK demod; but when we're an
@@ -69,13 +69,16 @@ begin
     end
 end
 
-// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
+// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.
-// we would add/sub at most 32 times adc_d, the signed result can be held in 14 bits. 
-reg signed [13:0] corr_i_accum;
-reg signed [13:0] corr_q_accum;
+// We would add at most 32 times the difference between unmodulated and modulated signal. It should
+// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
+// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
+reg signed [11:0] corr_i_accum;
+reg signed [11:0] corr_q_accum;
+// we will report maximum 8 significant bits
 reg signed [7:0] corr_i_out;
 reg signed [7:0] corr_q_out;
 // clock and frame signal for communication to ARM
@@ -99,16 +102,16 @@ begin
     begin
         if(snoop)
 			begin
-				// Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
-				corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
-				corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
+			// Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
+            corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
+            corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
 				after_hysteresis_prev_prev <= after_hysteresis;
 			end
         else
 			begin
-				// 8 most significant bits of tag signal
-				corr_i_out <= corr_i_accum[13:6];
-				corr_q_out <= corr_q_accum[13:6];
+            // 8 bits of tag signal
+            corr_i_out <= corr_i_accum[11:4];
+            corr_q_out <= corr_q_accum[11:4];
 			end
 
         corr_i_accum <= adc_d;

fpga/hi_read_tx.v

@@ -12,7 +12,7 @@ module hi_read_tx(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,
-    shallow_modulation, speed, power
+    shallow_modulation
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -23,46 +23,36 @@ module hi_read_tx(
     input cross_hi, cross_lo;
     output dbg;
     input shallow_modulation;
-    input [1:0] speed;
-    input power;
 
+// low frequency outputs, not relevant
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;
+	
 // The high-frequency stuff. For now, for testing, just bring out the carrier,
 // and allow the ARM to modulate it over the SSP.
 reg pwr_hi;
 reg pwr_oe1;
-reg pwr_oe2;
 reg pwr_oe3;
 reg pwr_oe4;
+
 always @(ck_1356megb or ssp_dout or shallow_modulation)
-begin
-if (power)
 begin
     if(shallow_modulation)
     begin
         pwr_hi <= ck_1356megb;
-        pwr_oe1 <= ~ssp_dout;
-        pwr_oe2 <= ~ssp_dout;
-        pwr_oe3 <= ~ssp_dout;
-        pwr_oe4 <= 1'b0;
+        pwr_oe1 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= ~ssp_dout;
     end
     else
     begin
         pwr_hi <= ck_1356megb & ssp_dout;
         pwr_oe1 <= 1'b0;
-        pwr_oe2 <= 1'b0;
         pwr_oe3 <= 1'b0;
         pwr_oe4 <= 1'b0;
     end
 end
-else
-begin
-       pwr_hi <= 1'b0;
-        pwr_oe1 <= 1'b0;
-        pwr_oe2 <= 1'b0;
-        pwr_oe3 <= 1'b0;
-        pwr_oe4 <= ~ssp_dout;
-end    
-end
+
 
 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
 // for the synchronous serial port.
@@ -72,7 +62,7 @@ reg [6:0] hi_div_by_128;
 always @(posedge ck_1356meg)
     hi_div_by_128 <= hi_div_by_128 + 1;
 
-assign ssp_clk = speed[1]? (speed[0]? hi_div_by_128[3]: hi_div_by_128[4]) : (speed[0]? hi_div_by_128[5]: hi_div_by_128[6]);
+assign ssp_clk = hi_div_by_128[6];
 
 reg [2:0] hi_byte_div;
 
@@ -89,14 +79,13 @@ assign adc_clk = ck_1356meg;
 reg after_hysteresis;
 always @(negedge adc_clk)
 begin
-    if(& adc_d[7:4]) after_hysteresis <= 1'b1;
+    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
 end
 
 
 assign ssp_din = after_hysteresis;
 
-assign pwr_lo = 1'b0;
 assign dbg = ssp_din;
 
 endmodule

fpga/hi_sniffer.v

@@ -17,11 +17,8 @@ module hi_sniffer(
     output dbg;
     input xcorr_is_848, snoop, xcorr_quarter_freq; // not used.
 
-    
-// let's try hi-pass
-
 // We are only snooping, all off.
-assign pwr_hi  = ck_1356megb & xcorr_quarter_freq;//1'b0;
+assign pwr_hi  = 1'b0;
 assign pwr_lo  = 1'b0;
 assign pwr_oe1 = 1'b0;
 assign pwr_oe2 = 1'b0;
@@ -32,12 +29,8 @@ reg ssp_frame;
 reg [7:0] adc_d_out = 8'd0;
 reg [2:0] ssp_cnt = 3'd0;
 
-
-reg [12:0] avg=13'd0;
-
-assign adc_clk = ck_1356megb;
-assign ssp_clk = ~ck_1356megb;
-
+assign adc_clk = ck_1356meg;
+assign ssp_clk = ~ck_1356meg;
 
 always @(posedge ssp_clk)
 begin
@@ -48,9 +41,7 @@ begin
 
     if(ssp_cnt[2:0] == 3'b000) // set frame length
         begin
-           // adc_d_out[7:0] <= (alias_buf>>>3) +8'd126;//( $signed(adc_d-adc_d_old)>1 | $signed(adc_d_old-adc_d)>1)?  alias_buf+adc_d-adc_d_old:alias_buf; //alias_buf[11:3]+8'd126;//adc_d;
-           // adc_d_out[7:0]<=adc_d;
-            adc_d_out[7:0] <=adc_d;//-(avg>>3) +8'd126;
+            adc_d_out[7:0] <= adc_d;
             ssp_frame <= 1'b1;
         end
     else